Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Abstract: Methods and systems for forming holes in a substrate using dewetting coating are described herein.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed.

Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarly, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of functionalized nanoparticles on a substrate by immersing the substrate in at least one of a solvent and a polymer matrix, wherein at least one of the solvent and the polymer matrix comprises a plurality of functionalized nanoparticles; and forming a second layer of functionalized nanoparticles on the first layer of functionalized particles, wherein there is a gradient in a property between the first layer and the second layer.

Abstract: In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed.

Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.

Abstract: Methods for forming traces/lines and interconnects on substrates and devices and systems thereof of herein disclosed. In some embodiments, an activator layer is deposited on a surface of a substrate. Pick-up lithography using a pre-patterned lithographic stamp, ultraviolet lithography or like methods are used to selectively remove portions of the activator layer to form a pattern on the surface of the substrate. Electroless metal deposition is then applied to the surface of the substrate to form a metal pattern selectively on the remaining activator layer. Electroless plating can then be used to form traces/lines and interconnects in dimensions of less than 10 micrometers.

Abstract: Methods and systems for forming holes in a substrate using dewetting coating are described herein.