Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.

Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.

Abstract: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

Abstract: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

Abstract: A multi-port memory array is tested by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array may be performed sequentially or in parallel. Comparator circuits are effectively disabled during normal processor operations. By simultaneously writing and/or reading data via multiple ports, latent electrical marginalities may be exposed. In addition, writing test patterns using multiple write ports and reading the patterns using multiple read ports significantly reduces test time during semiconductor manufacturing tests.

Abstract: An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.

Abstract: A bus-clock-speed-independent apparatus and method of wrap input/output (I/O) testing of an I/O interface is provided. Launch data is launched in response to a launch clock. A capture clock is derived from the launch clock by delaying the launch clock through a programmable delay. Launch data is wrapped through the I/O interface buffers and captured in response to the capture clock. A initial value of the programmable delay is selected and successively increased or decreased until the launch data is just captured, or just fails to be captured, respectively. The value of the programmable delay when this occurs provides a measure of the limiting speed of the I/O interface.

Abstract: A temperature sensor having a process compensated current generator (37) for use in a temperature sensing circuit (35) and a current comparator (40). The current generated in reference current generator (36) provides a complementary distortion to balance the effect introduced by processing into the two circuits which make up temperature dependent current generator (38). The generator generates two currents which are used to measure temperature changes. The generator including both PFET and bipolar devices, where the generator compensates for variations in processing conditions. According to one embodiment, the temperature sensor includes a process compensation generator which provides an indicator as a function of at least one processing parameter and a current generator which adjusts the currents according to the indicator.

Abstract: Series-connected stacked PFETS are employed in an off-chip driver output stage. When the output driver is enabled, the gate of the PFET transistor directly connected to the output is biased by a latch at a voltage level of either one threshold voltage above ground or one threshold voltage below the power supply, depending on the data signal. This provides overvoltage protection even for overshoots and undershoots of one threshold voltage or less, and provides overvoltage protection below the threshold voltages required to activate conventional overvoltage protection devices. Tight tolerances for maximum gate voltages may thus be achieved, and smaller devices having thinner gate oxides utilized in the off-chip drivers of a processor or other device.