Abstract: A circuit comprises P-channel and N-channel field effect transistors. A conduction electrode, such as a drain, of one of the transistors is coupled to a conduction electrode of the other transistor. Means are provided for ensuring that the currents in the transistors when changing state, and hence the rise and fall times of an output signal of the transistors, are substantially equal. Preferably, the ensuring means comprises the channel length of the P-channel transistor being smaller than that of the N-channel device. Alternately, either the doping level or the width of the P-channel device can be greater than that of the N-channel device.

Abstract: A continuously variable phase shifter for the phase range from 0.degree. to 90.degree., switchable phase shifters switchable between 0.degree. and 90.degree. and a continuously variable phase shifter for the phase shift range of 0.degree. to 360.degree. are disclosed. Each of the phase shifters relies on dual gate FET devices to provide the required phase shift in a compact structure while providing sufficient gain to avoid signal losses through the phase shifter. The transmission phase shift through a dual gate FET device is controlled by the DC bias on its second gate and by the type of reactive termination on that gate. A capacitive termination provides a transmission phase shift which is substantially independent of bias while an inductive termination provides a transmission phase shift which varies substantially linearly with bias voltage over a substantial range of bias voltage.

Abstract: Microwave couplers such as power splitters and combiners for coupling a common terminal to two branch terminals are disclosed which are compact and provide gain. Each leg of the branching circuit comprises a dual gate FET device. The dual gate FET device has its first gate connected to receive an input signal, its second gate biased and terminated in accordance with the phase shift desired from that FET device and its drain coupled to provide an output signal. Where equal phases are desired from both legs, the second gates of all of the FET devices are capacitively terminated. Where a differential phase shift is desired over the two legs, the second gate of the FET device in one leg is capacitively terminated and the second gate of the FET device in the other leg is inductively terminated. The bias voltages on the second gates are preferably selected to produce the same gain for both.

Abstract: A one port-to-M port passive signal power divider circuit (or combiner circuit) where M>2 and .noteq. 2.sup.N, M and N are integers, includes M - 1 two-way in-phase passive power dividers having a signal delay D through each path in one or more delay devices having delay D. Each output of each two-way power divider is coupled to an input of another power divider, a delay line or an output port, the arrangement being such that the delay through all ports of the power divider are equal. In accordance with a further embodiment of the invention the outputs of a passive power divider are connected to two-way switches using active components. The switches under control of a control circuit are utilized to switch the input signal to the power divider to any one of 2.multidot.M output terminals of the switches.

Abstract: A plurality of FET or other amplifiers are connected between respective outputs of an N output port power divider network and respective inputs of an N input power combining network in a variable power amplifier system. A gate bias is selectively supplied to each of the amplifiers which is either at a first value to cause the amplifier to amplify or at a second value to cause the amplifier to be cut off and therefore to not dissipate any DC power. The number of amplifiers receiving the first potential is determinative of the amount of power amplification of the variable power amplifier.

Abstract: The threshold comparator includes a switching FET including a gate electrode and a load FET connected in series across a source of potential where the load FET is configured to provide a saturation current less than that of the switching FET with a first input level to the gate electrode and provide a saturation current greater than that of the switching FET with a second input level to the gate electrode. The output voltage of the switching FET changes value abruptly when the input level at its gate electrode attains the second input level where the saturation current in the switching FET is less than the saturation current of the load FET.

Abstract: An exclusive-OR circuit includes a first pair of field effect transistors (FETs), series coupled to a transferred electron logic device (TELD) and a second pair of FETs, arranged as an inhibit circuit. The second pair of FETs is either coupled in series with the first pair of FETs and TELD or in a parallel-serial relationship therewith in accordance with different embodiments of the invention. When a signal of a given polarity and a signal indicative of that signal are applied respectively to only one gate of each pair of FETs, the TELD produces an output signal. When a signal of a given polarity and a signal indicative of that signal are applied respectively to both gates of each pair of FETs, the second pair of FETs inhibits the TELD from producing an output signal.

Abstract: A field effect transistor (FET) is connected in series to a transferred electron logic device (TELD), the TELD being a non-linear load resistor for the FET. The current thresholding property of the TELD and the saturation characteristics of the FET are utilized to produce an output pulsed signal of substantial voltage gain with fast rise time and short pulse width. An output electrode is capacitively coupled to the TELD to provide an output pulsed signal of alternating polarity for direct interconnection of devices in cascaded circuits.