Abstract: A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency bit field of a load instruction to create a Distance of Dependency (DoD) bit field. The DoD bit field holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by the DoD bit field. In the preferred embodiment, an acknowledgement is sent to the processing unit when the time specified is available in the RTOQ.

Abstract: A system for time-ordered issuance of instruction fetch requests (IFR). More specifically, the system enables just-in-time delivery of instructions requested by an IFR. The system consists of a processor, an L1 instruction cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency field of an IFR to create a Time of Dependency (ToD) field. The ToD field holds a time dependency value which is utilized to order the IFR in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The IFR is issued from RTOQ to the L1 instruction cache so that the requested instruction is fetched from the L1 instruction cache at the time specified by the ToD value. In an alternate embodiment the ToD is converted to a CoD and the instruction is fetched from a lower level cache at the CoD value.

Abstract: A method for converting a distance of dependency (DoD) value to a cycle of dependency (CoD) value is disclosed. The method comprises the steps of (i) simulating a dependency system timer (DST) on a data processing system, with the DST having a present time measured in cycles and a period, (ii) adding a DoD value of N bits to the present time to yield a resulting time of the least significant N bits of said adding step, and (iii) creating the CoD value by appending a carry over of the adding step to the resulting time, where when the carry over is not equal to zero, the carry over signals a user of the CoD value to wait until a next period before the CoD value should be applied. In one embodiment, the carry-over value is added to the value corresponding to a respective alternating period to yield an even/odd bit which determines the period.

Abstract: A method for ordering the time of issuing of a load instruction from a lower level (L2) cache controller to its L2 cache in a data processing system to enable delivery of a load data at a time it is required by its downstream dependency is disclosed. The method comprises the steps of (i) determining a cycle of dependency (CoD) of the load data, where the CoD corresponds to an exact synchronized timer (ST) time, measured in cycles, on which said data is required by said downstream dependency from the L2 cache, and (ii) issuing the load instruction to said L2 cache at said time to synchronize a providing of said data to a pipeline of a system resource with a request by its downstream dependency. In the preferred embodiment of the invention, a distance of dependency (DoD) value is first appended to the load instruction. The DoD value is then converted to a CoD value when a miss occurs at the internal (L1) cache.

Abstract: A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time dependency value to the load instruction, where the time dependency value corresponds to the desired time, (ii) means for verifying that said desired time is available for loading said data, and (iii) means for sending an acknowledgement (ACK) when the desired time is available, where a processor reserves the system resources for accepting the data at the desired time in response to the ACK.

Abstract: A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates a plurality of architected time dependency fields of a load instruction to create a plurality of dependency fields. The dependency fields holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by one of the dependency fields. The dependency fields are prioritized so that the cycle corresponding to the highest priority field which is available is utilized.