Abstract: A memory has input buffer which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer includes an input inverter with hysteresis as well as a cross coupled latched for avoiding problems with a slow moving input signal. The cross coupled latch is a NAND gate latch to provide for a quick logic low to logic high transition which is favorable for quick transition detection. A second inverter provides a feedback signal to a feedback transistor which provides hysteresis for the first inverter. A load is placed in series with the feedback transistor for use in obtaining the desired hysteresis. The feedback transistor can thus have a minimum gate area to minimize the capacitance added by the feedback transistor to the output of the second inverter while the load can be varied as desired for optimizing the hysteresis.