Abstract: Systems, methods, and apparatus for implementing hardware flow control between devices coupled through a serial peripheral interface. A method for transmitting information using a serial peripheral interface includes initiating an exchange of data over one or more data lines of a serial peripheral interface bus by asserting a first voltage state on a slave select line, transmitting data and clock signals over the serial peripheral interface bus while the slave select line remains at the first voltage state, refraining from transmitting data and clock signals over the serial peripheral interface bus when the slave select line transitions to a second first voltage state, receiving data at a slave device into a receive buffer while the slave select line remains at the first voltage state, and asserting the second voltage state on the slave select line when occupancy of the receive buffer reaches or exceeds a threshold occupancy level.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes encoding virtual GPIO signals or messages into a data packet, determining a maximum latency requirement for transmitting the data packet over the communication link, providing a command code header indicating a packet type to be used for transmitting the data packet over the communication link, and transmitting the command code header and the data packet over the communication link in a packet selected to satisfy the maximum latency requirement. A protocol for transmitting the data packet may be determined based on the maximum latency requirement and one or more attributes of protocols available for use on the communication link. In one example, the communication link includes a serial bus and the available protocols include I2C, I3C, and/or RFFE protocols.

Abstract: Systems, methods, and apparatus for data communication are provided. An apparatus maybe configured to generate a mask field in a packet to be transmitted through an interface to a slave device, the mask field having a first number of bits, provide a control-bit field in the packet, the control-bit field having a second number of bits, where the second number of bits is less than the first number of bits, and transmit the packet through the interface. The packet may be addressed to a control register of the slave device. The control register may have the first number of bits. Each bit in the control-bit field may correspond to a bit of the control register that is identified by the mask field.

Abstract: Enhanced communications over a Universal Serial Bus (USB) Type-C cable are disclosed. In one aspect, a link control circuit is provided in a USB host to enable one or more communication circuits in the USB host to transmit and receive protocol-specific data over a sideband use (SBU) interface according to communication protocols that may or may not be USB compliant. In another aspect, the link control circuit is provided in a USB client to enable one or more communication circuits in the USB client to transmit and receive protocol-specific data over the SBU interface according to communication protocols that may or may not be USB compliant. By configuring the USB host and the USB client to support multi-protocol communications via the SBU interface, it is possible to enable more flexible architectural design in mobile communication devices for enhanced performance and reduced costs.

Abstract: Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB), compares the MSB to a receiver base address maintained in a shadow register, compares the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register, and sends the datagram to the receiver via the bus interface when: the MSB is equal to the receiver base address maintained in the shadow register, and the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.

Abstract: Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a register address, detects whether the register address is within a high data rate (HDR) access address range, and sends a payload of the datagram to the receiver according to a HDR mode when the register address is within the HDR access address range. In another configuration, the transmitter generates a datagram including at least a command field and a data field, sends the command field to the receiver according to a single data rate (SDR) mode, wherein the command field indicates a transition to a high data rate (HDR) mode for sending the data field, and sends the data field to the receiver according to the HDR mode.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

Abstract: A modified serial peripheral interface (SPI) is provided in each of a master device and a plurality of slave devices that does not use a slave select line. The master device may thus engage in full-duplex serial communication with each slave device through an SPI MOSI line, an SPI MISO line, and an SPI clock line.

Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.

Abstract: A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.

Abstract: A bit-by-bit error correction technique is disclosed that divides each bit transmission into an acknowledgment phase, an error correction phase, and a transmission phase.

Abstract: A robotic system includes a set of manipulators selectively and operatively coupled via a common interconnect to a control module. The control module is responsive to parameters recorded while performing a defined task with members selected from the set of manipulators. The parameters are applied to a selection engine that identifies an optimal member from the set of manipulators for a defined task.

Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation to transmit a plurality of GPIO signals as virtual GPIO signals.

Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a hit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message, Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Abstract: Methods, devices, systems, and non-transitory process-readable storage media for a computing device of an autonomous vehicle to generate real-time mappings of nearby vehicles. An embodiment method executed by a computing device may include operations for obtaining origin point coordinates via a first satellite-based navigation functionality, obtaining termination point coordinates via a second satellite-based navigation functionality, calculating a unit vector based on the obtained origin point coordinates and the obtained termination point coordinates, identifying a position, a direction, and an occupancy of the autonomous vehicle based on the obtained origin point coordinates, the calculated unit vector, and stored vehicle dimensions data (e.g., length, width, height), and transmitting a message using DSRC with the origin point coordinates, the stored vehicle dimensions data, and data for identifying the vehicle's direction.

Abstract: A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.