Abstract: A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) over one portion of a substrate, while leaving portions the polysilicon layer (31, 33, 29) intact over other portions of the substrate (22b). Multi-layer metal electrodes are deposited and patterned to form a rectifying schottky contact to the exposed single crystal region (22a), and to form an ohmic contact to the exposed polysilicon (31, 33, 29).

Abstract: A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well as emitter (30) and collector (32) regions which are interchangeable, greatly easing layout of integrated circuits using the transistor structure (10).

Abstract: A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well as emitter (30) and collector (32) regions which are interchangeable, greatly easing layout of integrated circuits using the transistor structure (10).

Abstract: A method of forming vertical trench inductor (10) includes providing a layer (11) and forming a plurality of trenches (12) vertically therein. The trenches (12) are filled with a conductive material (16) and etched using a photolithographically defined mask (17). The etching produces a conductive liner (18) covering two sidewalls (13) and a bottom surface (14) of the trench (12). A second conductive layer is formed and patterned to couple the conductive liner (18) covering a sidewall (13) of a first trench (12) to the conductive liner (18) of an opposite sidewall (13) of an adjacent trench (12) to form an inductive coil.

Abstract: A method of forming vertical trench inductor (10) includes providing a layer (11) and forming a plurality of trenches (12) vertically therein. The trenches (12) are filled with a conductive material (16) and etched using a photolithographically defined mask (17). The etching produces a conductive liner (18) covering two sidewalls (13) and a bottom surface (14) of the trench (12). A second conductive layer is formed and patterned to couple the conductive liner (18) covering a sidewall (13) of a first trench (12) to the conductive liner (18) of an opposite sidewall (13) of an adjacent trench (12) to form an inductive coil.

Abstract: A dual-gate gallium arsenide power MESFET chip comprising a source region surrounded by a first gate, a second surrounding the first gate, a drain region juxtaposed to said second gate, and a shorting bar which couples the second gate to the source region. This combination, used in a multi-fingered application, provides a reverse breakdown voltage substantially higher than prior art devices.