Abstract: Systems and methods for cross platform configuration are described herein. The platform may receive selections for software programs or operating system configurations and selections of installation settings. A blueprint file is generated to specify the software programs or operating systems that are selected. In addition, the blueprint file may specify different installation settings and configuration settings. The blueprint file is stored in a repository and may be applied to one or more target devices. When applied, a task schedule is generated, where the task schedule prioritizes installations specified in a blueprint file. In addition, the task schedule specifies various provider identifiers to perform the installation(s).

Abstract: Methods, systems, and devices for data management are described. A data management system (DMS) may receive a request to access metadata stored in a distributed metadata repository. The request may have a first semantic format compatible with a first version of the distributed metadata repository. The DMS may translate the first semantic format of the request to a second semantic format compatible with a second version of the distributed metadata repository. The DMS may perform the semantic translation according to a label in the request. Accordingly, the DMS may determine whether a current version of the metadata corresponds to the first version of the distributed metadata repository or the second version of the distributed metadata repository, and may access the metadata in the distributed metadata repository based on the request and the current version of the metadata.

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

Abstract: Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.

Abstract: The disclosure introduces a level-shifter including a boost circuit that provides a “one-shot” pulse (a self-annihilating pulse) with the transitioning edge of the output signal. The pulse can be used to produce a faster output rise time and reduce the overall footprint of a level-shifter compared to conventional level-shifters. In one example the level-shifter includes: (1) input circuitry configured to receive one or more input signals from one or more input voltage domains, (2) output circuitry configured to provide an output signal, based on at least one of the one or more input signals, for an output voltage domain, wherein an operating voltage of the output voltage domain is greater than an operating voltage of the one or more input voltage domains, and (3) a boost circuit connected to the output circuitry and configured to provide a current pulse for a transition edge of the output signal.

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

Abstract: Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.

Abstract: Methods, systems, and devices for data management are described. A data management system (DMS) may receive a request to access metadata stored in a distributed metadata repository. The request may have a first semantic format compatible with a first version of the distributed metadata repository. The DMS may translate the first semantic format of the request to a second semantic format compatible with a second version of the distributed metadata repository. The DMS may perform the semantic translation according to a label in the request. Accordingly, the DMS may determine whether a current version of the metadata corresponds to the first version of the distributed metadata repository or the second version of the distributed metadata repository, and may access the metadata in the distributed metadata repository based on the request and the current version of the metadata.

Abstract: Some embodiments may obtain a natural language question, determine a context of the natural language question, and generate a first vector based on the natural language question using encoder neural network layers. Some embodiments may access a data table comprising column names, generate vectors based on the column names, and determine attention scores based on the vectors. Some embodiments may update the vectors based on the attention scores, generating a second vector based on the natural language question, determine a set of strings comprising a name of the column names and a database language operator based on the vectors. Some embodiments may determine a values based on the determined database language operator, the name, using a transformer neural network model. Some embodiments may generate a query based on the set of strings and the values.

Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

Abstract: The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.

Abstract: Some embodiments may perform operations of a process that includes obtaining a natural language text document and use a machine learning model to generate a set of attributes based on a set of machine-learning-model-generated classifications in the document. The process may include performing hierarchical data extraction operations to populate the attributes, where different machine learning models may be used in sequence. The process may include using a pre-trained Bidirectional Encoder Representations from Transformers (BERT) model augmented with a pooling operation to determine a BERT output via a multi-channel transformer model to generate vectors on a per-sentence level or other per-text-section level. The process may include using a finer-grain model to extract quantitative or categorical values of interest, where the context of the per-sentence level may be retained for the finer-grain model.

Abstract: Some embodiments may perform operations of a process that includes obtaining a natural language text document and use a machine learning model to generate a set of attributes based on a set of machine-learning-model-generated classifications in the document. The process may include performing hierarchical data extraction operations to populate the attributes, where different machine learning models may be used in sequence. The process may include using a pre-trained Bidirectional Encoder Representations from Transformers (BERT) model augmented with a pooling operation to determine a BERT output via a multi-channel transformer model to generate vectors on a per-sentence level or other per-text-section level. The process may include using a finer-grain model to extract quantitative or categorical values of interest, where the context of the per-sentence level may be retained for the finer-grain model.

Abstract: Multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.

Abstract: Methods, systems, and devices for data management are described. A data management system (DMS) may receive a request to access metadata stored in a distributed metadata repository. The request may have a first semantic format compatible with a first version of the distributed metadata repository. The DMS may translate the first semantic format of the request to a second semantic format compatible with a second version of the distributed metadata repository. The DMS may perform the semantic translation according to a label in the request. Accordingly, the DMS may determine whether a current version of the metadata corresponds to the first version of the distributed metadata repository or the second version of the distributed metadata repository, and may access the metadata in the distributed metadata repository based on the request and the current version of the metadata.

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: Some embodiments may obtain a natural language question, determine a context of the natural language question, and generate a first vector based on the natural language question using encoder neural network layers. Some embodiments may access a data table comprising column names, generate vectors based on the column names, and determine attention scores based on the vectors. Some embodiments may update the vectors based on the attention scores, generating a second vector based on the natural language question, determine a set of strings comprising a name of the column names and a database language operator based on the vectors. Some embodiments may determine a values based on the determined database language operator, the name, using a transformer neural network model. Some embodiments may generate a query based on the set of strings and the values.

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

Abstract: Some embodiments may obtain a natural language question, determine a context of the natural language question, and generate a first vector based on the natural language question using encoder neural network layers. Some embodiments may access a data table comprising column names, generate vectors based on the column names, and determine attention scores based on the vectors. Some embodiments may update the vectors based on the attention scores, generating a second vector based on the natural language question, determine a set of strings comprising a name of the column names and a database language operator based on the vectors. Some embodiments may determine a values based on the determined database language operator, the name, using a transformer neural network model. Some embodiments may generate a query based on the set of strings and the values.

Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.