Patents by Inventor Lalit SHOKEEN

Lalit SHOKEEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hard mask etch and dielectric etch aware overlap for via and metal layers
    Patent number: 9817927
    Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guo Xiang Ning, Yuping Ren, David Power, Lalit Shokeen, Chin Teong Lim, Paul W. Ackmann, Xiang Hu
  • HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL LAYERS
    Publication number: 20170061044
    Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Guo Xiang NING, Yuping REN, David POWER, Lalit SHOKEEN, Chin Teong LIM, Paul W. ACKMANN, Xiang HU