Abstract: A line segment is rendered by two triangles joined by their hypotenuses. A graphics processing system includes a lookup table that contains a plurality of values representing reciprocal square roots for normal vectors to a corresponding plurality of line segments. The dot product of a normal vector to the line segment is scaled by a scaling factor and input to the lookup table. The scaling factor has a trivial/simple square root and is a power of 2 so that multiplication of binary values may be performed by shifting. A value is output from the lookup table representing a reciprocal square root of the normal vector to the line segment. A half unit normal vector to the line segment is determined based on the normal vector to the line segment and the output value and is used to determine the two triangles for rendering the line segment.

Abstract: An apparatus, a method, a method of manufacturing and apparatus, and a method of constructing an integrated circuit are provided.

Abstract: A clip-cull-viewport (CCV) unit manages information associated with vertices of a primitive as the primitive passes through the CCV unit. The CCV unit includes an index cache and a cache-status table. Vertices of a received primitive are stored in locations within the index cache based on attribute and index fields of the primitive. If a vertex is a reused vertex of another primitive that matches a valid entry in the cache-status table and if the primitive survives being culled, the valid entry in the cache-status table is preserved, the attribute field of the primitive is set to indicate that the vertex is a reused vertex, and the primitive is sent to an output interface for a downstream unit. Otherwise, the attribute field is set to indicate that the vertex is not reused, and the primitive is sent to the output interface for the downstream unit.

Abstract: A clip-cull-viewport (CCV) unit manages information associated with vertices of a primitive as the primitive passes through the CCV unit. The CCV unit includes an index cache and a cache-status table. Vertices of a received primitive are stored in locations within the index cache based on attribute and index fields of the primitive. If a vertex is a reused vertex of another primitive that matches a valid entry in the cache-status table and if the primitive survives being culled, the valid entry in the cache-status table is preserved, the attribute field of the primitive is set to indicate that the vertex is a reused vertex, and the primitive is sent to an output interface for a downstream unit. Otherwise, the attribute field is set to indicate that the vertex is not reused, and the primitive is sent to the output interface for the downstream unit.

Abstract: An apparatus, a method, a method of manufacturing and apparatus, and a method of constructing an integrated circuit are provided.

Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Abstract: A duty cycle correction circuit capable of generating a clock signal having good (e.g., approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.

Abstract: A duty cycle correction circuit capable of generating a clock signal having good (e.g., approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.