Patents by Inventor Lan Chiang
Lan Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10348431Abstract: A method of small cell discovery and RSRP/RSRQ measurements in OFDM/OFDMA systems is proposed. A discovery reference signal (DRS) with low transmission frequency is introduced to support small cell detection within a short time, multiple small cell discovery, and accurate measurement of multiple small cells. The DRS consists of one or multiple reference signal types with the functionalities including timing and frequency synchronization, cell detection, RSRP/RSSI/RSRQ measurements, and interference mitigation. RE muting is configured for the DRS to reduce interference level from data to DRS for discovery and RSRP/RSRQ measurements for small cells.Type: GrantFiled: July 24, 2017Date of Patent: July 9, 2019Assignee: HFI Innovation INC.Inventors: Pei-Kai Liao, Hsiao-Lan Chiang, Chien-Chang Li, Xiangyang Zhuang
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Patent number: 9966429Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: GrantFiled: August 6, 2015Date of Patent: May 8, 2018Assignee: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Publication number: 20170324499Abstract: A method of small cell discovery and RSRP/RSRQ measurements in OFDM/OFDMA systems is proposed. A discovery reference signal (DRS) with low transmission frequency is introduced to support small cell detection within a short time, multiple small cell discovery, and accurate measurement of multiple small cells. The DRS consists of one or multiple reference signal types with the functionalities including timing and frequency synchronization, cell detection, RSRP/RSSI/RSRQ measurements, and interference mitigation. RE muting is configured for the DRS to reduce interference level from data to DRS for discovery and RSRP/RSRQ measurements for small cells.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Pei-Kai Liao, Hsiao-Lan Chiang, Chien-Chang Li, Xiangyang Zhuang
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Patent number: 9749075Abstract: A method of small cell discovery and RSRP/RSRQ measurements in OFDM/OFDMA systems is proposed. A discovery reference signal (DRS) with low transmission frequency is introduced to support small cell detection within a short time, multiple small cell discovery, and accurate measurement of multiple small cells. The DRS consists of one or multiple reference signal types with the functionalities including timing and frequency synchronization, cell detection, RSRP/RSSI/RSRQ measurements, and interference mitigation. RE muting is configured for the DRS to reduce interference level from data to DRS for discovery and RSRP/RSRQ measurements for small cells.Type: GrantFiled: September 25, 2014Date of Patent: August 29, 2017Assignee: MEDIATEK INC.Inventors: Pei-Kai Liao, Hsiao-Lan Chiang, Chien-Chang Li, Xiangyang Zhuang
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Patent number: 9559797Abstract: A method of small cell discovery and RSRP/RSRQ measurements in OFDM/OFDMA systems is proposed. A discovery reference signal (DRS) with low transmission frequency is introduced to support small cell detection within a short time, multiple small cell discovery, and accurate measurement of multiple small cells. The DRS consists of one or multiple reference signal types with the functionalities including timing and frequency synchronization, cell detection, RSRP/RSSI/RSRQ measurements, and interference mitigation. RE muting is configured for the DRS to reduce interference level from data to DRS for discovery and RSRP/RSRQ measurements for small cells.Type: GrantFiled: September 25, 2014Date of Patent: January 31, 2017Assignee: MEDIATEK INC.Inventors: Pei-Kai Liao, Hsiao-Lan Chiang, Chien-Chang Li, Xiangyang Zhuang
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Publication number: 20160293592Abstract: A bidirectional transient voltage suppressor includes a semiconductor substrate having a first conductivity type; a first epitaxial semiconductor layer having a second conductivity type formed on a first side of the semiconductor substrate; a second semiconductor layer having the first conductivity type formed on the first epitaxial semiconductor layer; and a first and second metallization layers disposed on a second side of the semiconductor substrate and the second semiconductor layer, respectively.Type: ApplicationFiled: March 31, 2015Publication date: October 6, 2016Inventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Cheng-Hao Chang
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Patent number: 9331142Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: GrantFiled: August 6, 2015Date of Patent: May 3, 2016Assignee: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Patent number: 9202935Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: GrantFiled: October 1, 2013Date of Patent: December 1, 2015Assignee: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Publication number: 20150340458Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Publication number: 20150340431Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Patent number: 9041188Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.Type: GrantFiled: November 10, 2012Date of Patent: May 26, 2015Assignee: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
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Publication number: 20150092655Abstract: A method of small cell discovery and RSRP/RSRQ measurements in OFDM/OFDMA systems is proposed. A discovery reference signal (DRS) with low transmission frequency is introduced to support small cell detection within a short time, multiple small cell discovery, and accurate measurement of multiple small cells. The DRS consists of one or multiple reference signal types with the functionalities including timing and frequency synchronization, cell detection, RSRP/RSSI/RSRQ measurements, and interference mitigation. RE muting is configured for the DRS to reduce interference level from data to DRS for discovery and RSRP/RSRQ measurements for small cells.Type: ApplicationFiled: September 25, 2014Publication date: April 2, 2015Inventors: Pei-Kai Liao, Hsiao-Lan Chiang, Chien-Chang Li, Xiangyang Zhuang
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Publication number: 20150091136Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: Vishay General Semiconductor LLCInventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Publication number: 20150092582Abstract: A method of small cell discovery and RSRP/RSRQ measurements in OFDM/OFDMA systems is proposed. A discovery reference signal (DRS) with low transmission frequency is introduced to support small cell detection within a short time, multiple small cell discovery, and accurate measurement of multiple small cells. The DRS consists of one or multiple reference signal types with the functionalities including timing and frequency synchronization, cell detection, RSRP/RSSI/RSRQ measurements, and interference mitigation. RE muting is configured for the DRS to reduce interference level from data to DRS for discovery and RSRP/RSRQ measurements for small cells.Type: ApplicationFiled: September 25, 2014Publication date: April 2, 2015Inventors: Pei-Kai Liao, Hsiao-Lan Chiang, Chien-Chang Li, Xiangyang Zhuang
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Patent number: 8796840Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: GrantFiled: March 16, 2012Date of Patent: August 5, 2014Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20140131842Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.Type: ApplicationFiled: November 10, 2012Publication date: May 15, 2014Applicant: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
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Patent number: 8252633Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.Type: GrantFiled: February 22, 2011Date of Patent: August 28, 2012Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20120168932Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: ApplicationFiled: March 16, 2012Publication date: July 5, 2012Applicant: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20120082269Abstract: A method for delay spread approximation used in a wireless communication system comprises the steps of: retrieving a plurality of pilot symbols from a channel of a wireless communication system; calculating at least one parameter representing the shape of the frequency response of the channel according to the values and the relative positions of the pilot symbols; determining a representative parameter value according to the at least one parameter; and determining a delay spread value according to the representative parameter value.Type: ApplicationFiled: December 23, 2010Publication date: April 5, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsiao Lan CHIANG, Pang An Ting, Jen Yuan Hsu
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Patent number: 8138597Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: GrantFiled: November 4, 2010Date of Patent: March 20, 2012Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng