Patents by Inventor Lan Chu Tan
Lan Chu Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150294924Abstract: A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.Type: ApplicationFiled: November 25, 2014Publication date: October 15, 2015Inventors: Zhigang Bai, Jinzhong Yao, Lan Chu Tan
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Publication number: 20150270206Abstract: A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (MCU) using either through silicon vias (TSVs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the MCU. These embodiments avoid the need to used bonds to electrically connect the pressure-sensing die to the MCU, thereby saving time, reducing size, and reducing cost.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Lan Chu Tan
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Publication number: 20150235924Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Inventors: Chee Seng Foong, Meng Kong Lye, Lan Chu Tan, Seng Kiong Teng
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Publication number: 20150200177Abstract: A semiconductor device is assembled where a signal redistribution layer is formed over a partially encapsulated semiconductor die. The distribution layer is formed by selectively coating a first electrical insulating layer over an active surface of the die and a surrounding portion of the encapsulation material, where die bonding pads on the active surface of the die are exposed through access apertures in the first electrical insulating layer. A layer of metallic powder is deposited onto the first insulating layer and then electrically conductive runners are formed from the layer of metallic powder. The runners are coated with a further electrical insulating layer. A mounting area of each runner is exposed through an external connection aperture. Solder balls may be attached to the mounting areas.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Inventors: CHEE SENG FOONG, Lan Chu Tan
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Publication number: 20150200180Abstract: A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Inventors: Kee Cheong Fam, Mohd Rusli Ibrahim, Lan Chu Tan
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Publication number: 20150201489Abstract: A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Inventors: Chee Seng Foong, Lan Chu Tan
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Publication number: 20150187728Abstract: In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Kesvakumar V.C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan
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Patent number: 9053972Abstract: A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.Type: GrantFiled: November 21, 2013Date of Patent: June 9, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Lan Chu Tan
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Publication number: 20150137354Abstract: A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Inventors: Chee Seng Foong, Lan Chu Tan
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Publication number: 20150097278Abstract: Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. A package body is formed by encapsulating the lead frame structure in which the frame members are positioned outside a side edge surface. The peripheral leads and the bottom face contact members project between the side edge surface of the package body and the frame members. The frame members are cut and the peripheral leads and the bottom face contact members are separated and electrically isolated from each other.Type: ApplicationFiled: August 14, 2014Publication date: April 9, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Zhigang Bai, Yin Kheng Au, Lan Chu Tan, Jinzhong Yao
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Publication number: 20150069537Abstract: A semiconductor sensor device has a MCU die and an acceleration-sensing die mounted on a die paddle of a lead frame. The MCU die is connected to leads of the lead frame with first bond wires and the acceleration-sensing die is connected to the MCU die with second bond wires. An interposer is flip-chip mounted on a top surface of the MCU die. The MCU die, acceleration-sensing die and a portion of the interposer are covered with a molding compound. A pre-packaged pressure sensor is flip-chip mounted on a top, exposed surface of the interposer. The interposer provides electrical connection between the pre-packaged pressure sensor and the MCU die.Type: ApplicationFiled: September 8, 2013Publication date: March 12, 2015Inventors: Wai Yew Lo, Stanley Job Doraisamy, Lan Chu Tan
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Publication number: 20150054099Abstract: A semiconductor sensor device is assembled using a pre-molded lead frame having first and second die flags. The first die flag includes a cavity. A pressure sensor die (P-cell) is mounted within the cavity and a master control unit die (MCU) is mounted to the second flag. The P-cell and MCU are electrically connected to leads of the lead frame with bond wires. The die attach and wire bonding steps are each done in a single pass. A mold pin is placed over the P-cell and then the MCU is encapsulated with a mold compound. The mold pin is removed leaving a recess that is next filled with a gel material. Finally a lid is placed over the P-cell and gel material. The lid includes a hole that that exposes the gel-covered active region of the pressure sensor die to ambient atmospheric pressure outside the sensor device.Type: ApplicationFiled: August 25, 2013Publication date: February 26, 2015Inventors: Kai Yun Yow, Poh Leng Eu, Chee Seng Foong, Navas Khan Oratti Kalandar, Lan Chu Tan
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Patent number: 8853058Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.Type: GrantFiled: June 22, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Kesvakumar V. C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan
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Patent number: 8802474Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.Type: GrantFiled: March 19, 2014Date of Patent: August 12, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jinzhong Yao, Wai Yew Lo, Lan Chu Tan, Xuesong Xu
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Publication number: 20140206124Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.Type: ApplicationFiled: March 19, 2014Publication date: July 24, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Jinzhong Yao, Wai Yew Lo, Lan Chu Tan, Xuesong Xu
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Patent number: 8716846Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.Type: GrantFiled: November 10, 2011Date of Patent: May 6, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jinzhong Yao, Wai Yew Lo, Lan Chu Tan, Xuesong Xu
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Patent number: 8669140Abstract: A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.Type: GrantFiled: April 4, 2013Date of Patent: March 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Kesvakumar V. C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan
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Patent number: 8643189Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.Type: GrantFiled: July 17, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Lan Chu Tan
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Publication number: 20140021621Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Lan Chu Tan
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Publication number: 20130344656Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Kesvakumar V.C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan