Patents by Inventor Lan-Da Van

Lan-Da Van has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7571414
    Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: August 4, 2009
    Assignee: National Chip Implementation Center, National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chih-Chyau Yang, Jing-Yang Jou, Kuen-Jong Lee, Lan-Da Van
  • Publication number: 20070294658
    Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 20, 2007
    Inventors: Chun-Ming Huang, Chih-Chyau Yang, Jing-Yang Jou, Kuen-Jong Lee, Lan-Da Van
  • Publication number: 20070109829
    Abstract: A dynamic time sequence control device and its method for a word matching circuit. The word matching circuit includes a first switch connected between an input voltage and a node to respond to a control signal generated by a pre-charging circuit so that within a pre-charging phase period a current is generated to flow through a capacitor to generate a charging voltage. The node is connected to multiple data memories and matching circuits so that the matching result can be outputted through the node. The dynamic time sequence control device includes a second switch connected between the first switch and the node.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 17, 2007
    Inventors: Chi-Sheng Lin, Chun-Ming Huang, Lan-Da Van, Nien-Hsiang Chang, Chun-Pin Lin, Chih-Hsien Hsu, Chau-Chin Wang