Patents by Inventor Lan Dinh Phan

Lan Dinh Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160216910
    Abstract: Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage.
    Type: Application
    Filed: April 4, 2016
    Publication date: July 28, 2016
    Inventor: Lan Dinh Phan
  • Patent number: 9305655
    Abstract: Reduced spatial redundancy of lower bits data provides data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory assists in restoring the data, using less than a full back up storage.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 5, 2016
    Assignee: Virtium Technology, Inc.
    Inventor: Lan Dinh Phan
  • Publication number: 20150317083
    Abstract: Flash memory devices can be implemented with deduplication mechanism through a synergetic deduplication mapping that combines the logical-to-physical address mapping of the flash memory devices with the deduplication mapping. A deduplication algorithm can be implemented in the application layer, which can freely communicate with the flash memory devices and perform computationally expensive operations.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Applicants: Virtium Technology, Inc., Lan Dinh Phan
    Inventor: Lan Dinh Phan
  • Publication number: 20150092487
    Abstract: Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Virtium Technology, Inc.
    Inventor: Lan Dinh Phan
  • Publication number: 20140181434
    Abstract: An embodiment is a technique to perform static wear leveling in a flash device. A first static block is popped from front of a first-in-first-out (FIFO) static pool when a static wear leveling condition is met. Data are copied from the first static block into an erased block to form a new block. The new block is pushed to end of the FIFO static pool. The static pool is part of a current static set and a next static set. Another embodiment is a technique to maintain a FIFO static pool. All valid data are consolidated when a data collection condition is met. An erased block is selected from a free set. All consolidated data are copied into the erased block to form a new block. The new block is pushed into the FIFO static pool.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: Virtium Technology, Inc.
    Inventors: Trevor Chau, Lan Dinh Phan
  • Publication number: 20140173175
    Abstract: An embodiment is a method and apparatus to provide an optimization of commands in a flash device. Commands sent by at least a top-level processor to a flash device are buffered in a buffer. The buffered commands are analyzed for an optimizing condition. The commands are aggregated if the optimizing condition is met. The aggregated commands are sent to the flash device.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Virtium Technology, Inc.
    Inventors: Ho-Fan Kang, Lan Dinh Phan