Abstract: The present disclosure provides an automatic driving test method. The method includes: acquiring test configuration information input by a user; generating test cases according to the test configuration information, and allocating the test cases to corresponding test types, wherein test types comprise a virtual simulation test, a whole vehicle in-loop test, a closed site test, and an open road test; and under each test type, testing a to be tested vehicle based on the corresponding test cases to obtain test results corresponding to each of the test type, and the test results comprise a simulation test result, a whole vehicle in-loop test result, a closed road test result, and an open road test result. Thus obtaining rich comprehensive test evaluation results makes the test results for autonomous vehicles more accurate.

Abstract: A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

Abstract: Provided are methods and compositions for promoting tissue (e.g., muscle) regeneration using one or more activators of fatty acid oxidation, such as one or more PPAR? activators. The methods and compositions described herein are also useful for promoting tissue growth, inducing proliferation of stem cells, inducing differentiation of tissuegenic cells (e.g., myogenic cells), and treating a disease or condition associated with a tissue (e.g., muscle), such as tissue injury, degeneration or aging, in an individual.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

Abstract: A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

Abstract: The present disclosure relates to crystal form A of 5-((4-ethylpiperazin-1-yl)methyl)-N-(5-fluoro-4-(4-fluoro-1-isopropyl-2-methyl-1H-benzo[d]imidazol-6-yl)pyridin-2-yl)pyrimidin-2-amine. The crystal form has a high purity, less residual solvent, high solubility and good stability; has good properties, fluidity and compressibility, and is convenient for production, detection, preparation of formulations, transportation and storage. The preparation method is easy to operate and is suitable for industrial production, and the crystal form can be used for treating and/or preventing diseases associated with CDK4/6 kinase-mediated cancers.

Abstract: A semiconductor device includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material. The ILD further includes a second portion doped with a large species material, wherein the second portion includes a first sidewall substantially perpendicular to a top surface of the substrate, and the second portion includes a second sidewall having a positive angle with respect to the first sidewall.

Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: The present disclosure relates to crystal form A of 5-((4-ethylpiperazin-1-yl)methyl)-N-(5-fluoro-4-(4-fluoro-1-isopropyl-2-methyl-1H-benzo[d]imidazol-6-yl)pyridin-2-yl)pyrimidin-2-amine. The crystal form has a high purity, less residual solvent, high solubility and good stability; has good properties, fluidity and compressibility, and is convenient for production, detection, preparation of formulations, transportation and storage. The preparation method is easy to operate and is suitable for industrial production, and the crystal form can be used for treating and/or preventing diseases associated with CDK4/6 kinase-mediated cancers.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A semiconductor device includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material. The ILD further includes a second portion doped with a large species material, wherein the second portion includes a first sidewall substantially perpendicular to a top surface of the substrate, and the second portion includes a second sidewall having a positive angle with respect to the first sidewall.

Abstract: A semiconductor device including a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material, a second portion doped with a large species material, and a third portion being undoped by the oxygen-containing material and the large species material.

Abstract: A backlight module includes a light source, a light guide plate and a light-adjusting member. A light source chromaticity is measured from light generated by the light source. The light guide plate has a light-incident surface and a light-emitting surface. Light generated by the light source enters the light guide plate and emits out from the light-emitting surface. With the light-adjusting member, a first light guide plate chromaticity is measured from the light-emitting surface. There is a first difference value between the first light guide plate chromaticity and the light source chromaticity. Without the light-adjusting member, a second light guide plate chromaticity is measured from the light-emitting surface. There is a second difference value between the second light guide plate chromaticity and the light source chromaticity. The first difference value is different from the second difference value.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A backlight module includes a light source, a light guide plate and a light-adjusting member. A light source chromaticity is measured from light generated by the light source. The light guide plate has a light-incident surface and a light-emitting surface. Light generated by the light source enters the light guide plate and emits out from the light-emitting surface. With the light-adjusting member, a first light guide plate chromaticity is measured from the light-emitting surface. There is a first difference value between the first light guide plate chromaticity and the light source chromaticity. Without the light-adjusting member, a second light guide plate chromaticity is measured from the light-emitting surface. There is a second difference value between the second light guide plate chromaticity and the light source chromaticity. The first difference value is different from the second difference value.

Abstract: A backlight module includes a light source, a light guide plate and a light-adjusting member. A light source chromaticity is measured from light generated by the light source. The light guide plate has a light-incident surface and a light-emitting surface. Light generated by the light source enters the light guide plate and emits out from the light-emitting surface. With the light-adjusting member, a first light guide plate chromaticity is measured from the light-emitting surface. There is a first difference value between the first light guide plate chromaticity and the light source chromaticity. Without the light-adjusting member, a second light guide plate chromaticity is measured from the light-emitting surface. There is a second difference value between the second light guide plate chromaticity and the light source chromaticity. The first difference value is different from the second difference value.