Patents by Inventor Lan Fang YU
Lan Fang YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476277Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.Type: GrantFiled: December 4, 2020Date of Patent: October 18, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Lei Ding, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
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Patent number: 11469248Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.Type: GrantFiled: December 4, 2020Date of Patent: October 11, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Lei Ding, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
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Publication number: 20210249436Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.Type: ApplicationFiled: December 4, 2020Publication date: August 12, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Lei DING, Jing GAO, Chuan YANG, Lan Fang YU, Ping YAN, Sen ZHANG, Bo XU
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Publication number: 20210118891Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.Type: ApplicationFiled: December 4, 2020Publication date: April 22, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Lei DING, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
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Patent number: 10868033Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.Type: GrantFiled: December 14, 2018Date of Patent: December 15, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Lei Ding, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
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Publication number: 20190148401Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.Type: ApplicationFiled: December 14, 2018Publication date: May 16, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: DING Lei, Jing GAO, Chuan YANG, Lan Fang YU, Ping YAN, Sen ZHANG, Bo XU