Patents by Inventor Lan-Feng Wang

Lan-Feng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12045179
    Abstract: A method for handling configuration data for an interconnection protocol within hibernation operation, a controller and an electronic device are provided. The method includes the following steps. In an electronic device, a hibernation entering indication signal indicating entering a hibernation state of the interconnection protocol is received. The electronic device has a memory and an index table, wherein the index table includes attribute identifiers corresponding to management information base (MIB) attributes, which belong to sub-layers of a link layer of the interconnection protocol and are required to be retained during hibernation. In response to the hibernation entering indication signal, MIB attribute storing is performed by a hardware protocol engine for implementing the link layer to read, for each one of the sub-layers, attribute data from the sub-layers according to the attribute identifiers from the index table sequentially and to write the attribute data sequentially to the memory.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: July 23, 2024
    Assignee: SK hynix inc.
    Inventors: Fu Hsiung Lin, Lan Feng Wang
  • Publication number: 20240241848
    Abstract: A controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. The controller is for a first device linkable to a second device according to the interconnection protocol. The controller includes a hardware protocol engine and a processing unit. The hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during Link Startup Sequence (LSS) capability exchange for the interconnection protocol. The processing unit is configured to be capable of modifying, during the LSS capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.
    Type: Application
    Filed: March 2, 2023
    Publication date: July 18, 2024
    Applicant: SK hynix Inc.
    Inventor: LAN FENG WANG
  • Publication number: 20240202142
    Abstract: A method for handling configuration data for an interconnection protocol within hibernation operation, a controller and an electronic device are provided. The method includes the following steps. In an electronic device, a hibernation entering indication signal indicating entering a hibernation state of the interconnection protocol is received. The electronic device has a memory and an index table, wherein the index table includes attribute identifiers corresponding to management information base (MIB) attributes, which belong to sub-layers of a link layer of the interconnection protocol and are required to be retained during hibernation. In response to the hibernation entering indication signal, MIB attribute storing is performed by a hardware protocol engine for implementing the link layer to read, for each one of the sub-layers, attribute data from the sub-layers according to the attribute identifiers from the index table sequentially and to write the attribute data sequentially to the memory.
    Type: Application
    Filed: March 1, 2023
    Publication date: June 20, 2024
    Applicant: SK hynix Inc.
    Inventors: FU HSIUNG LIN, LAN FENG WANG
  • Publication number: 20240121323
    Abstract: Method for control protocol frame transmission and electronic device are provided. The method comprises following operations. By the electronic device operating in an advanced line encoding mode and having a first burst from the electronic device to the other electronic device, the first burst is closed and a second burst is opened from the electronic device to the other electronic device for request frame transmission, wherein the electronic device operating in the advanced line encoding mode is configured to transmit data by using an advanced line encoding having an effective data rate larger than an effective data rate of 8b/10b encoding. By the electronic device, a request frame is transmitted in the second burst.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventors: LAN FENG WANG, WEN JYH LIN
  • Patent number: 11841756
    Abstract: A method for information configuration in power mode change for an interconnection protocol, a controller, and a storage device. The method can be used in a first device capable of linking to a second device according to the interconnection protocol. The method includes: while a hardware protocol engine of the first device for implementing a protocol layer of the interconnection protocol performs power mode change according to the protocol layer, generating a configuration indication signal to trigger a piece of firmware of the first device for performing information configuration for a physical layer of the interconnection protocol; in response to the configuration indication signal, performing the information configuration for the physical layer by the piece of firmware; and upon completion of the information configuration for the physical layer, informing, by the piece of firmware, the hardware protocol engine of the completion of the information configuration.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventors: Lan Feng Wang, Won Kyoo Lee
  • Patent number: 11716169
    Abstract: A method for error handling of an interconnection protocol, a controller and a storage device are provided. The method for error handling of an interconnection protocol is for use in a first device that is linkable to a second device according to the interconnection protocol, the method comprising: during or after a power mode change of a link between the first device and the second device: a) triggering, by the first device, a first line reset signal to the second device; b) performing, by the first device, suppression of detected rate overlap errors; and c) stopping the suppression of detected rate overlap errors after the first device receives a second line reset signal from the second device.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: August 1, 2023
    Assignee: SK hynix Inc.
    Inventors: Cheng Wei Yu, Wen Jyh Lin, Lan Feng Wang
  • Publication number: 20230188256
    Abstract: A method for error handling of an interconnection protocol, a controller and a storage device are provided. The method for error handling of an interconnection protocol is for use in a first device that is linkable to a second device according to the interconnection protocol, the method comprising: during or after a power mode change of a link between the first device and the second device: a) triggering, by the first device, a first line reset signal to the second device; b) performing, by the first device, suppression of detected rate overlap errors; and c) stopping the suppression of detected rate overlap errors after the first device receives a second line reset signal from the second device.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 15, 2023
    Applicant: SK hynix Inc.
    Inventors: CHENG WEI YU, WEN JYH LIN, LAN FENG WANG
  • Publication number: 20230073160
    Abstract: A clock generating device, a controller and a storage device. The clock generating device comprises: a clock generator counter outputting a clock trigger signal according to a clock period of each reference number of a reference clock; a compensation counter module outputting a compensation signal, the compensation counter module comprises: a first compensation counter outputting a first compensation clock according to a clock period of each first compensation number of the reference clock, the first compensation number is greater than the reference number, the compensation signal includes the first compensation clock; and a clock generator, when the compensation signal is in a first state, the clock generator generates a target clock signal according to the clock trigger signal; when the compensation signal is in a second state, the clock generator cancels a corresponding pulse in the clock trigger signal according to the compensation signal to generate the target clock signal.
    Type: Application
    Filed: December 22, 2021
    Publication date: March 9, 2023
    Applicant: SK hynix Inc.
    Inventor: LAN FENG WANG
  • Publication number: 20220283622
    Abstract: A method for information configuration in power mode change for an interconnection protocol, a controller, and a storage device. The method can be used in a first device capable of linking to a second device according to the interconnection protocol. The method includes: while a hardware protocol engine of the first device for implementing a protocol layer of the interconnection protocol performs power mode change according to the protocol layer, generating a configuration indication signal to trigger a piece of firmware of the first device for performing information configuration for a physical layer of the interconnection protocol; in response to the configuration indication signal, performing the information configuration for the physical layer by the piece of firmware; and upon completion of the information configuration for the physical layer, informing, by the piece of firmware, the hardware protocol engine of the completion of the information configuration.
    Type: Application
    Filed: December 22, 2021
    Publication date: September 8, 2022
    Applicant: SK hynix Inc.
    Inventors: LAN FENG WANG, WON KYOO LEE
  • Patent number: 7440405
    Abstract: A system and method for forwarding data packets with quality of service and rate control. A plurality of data packets are received from a plurality of sources. The header information of each data packet is extracted and compared against a plurality of tables, and then new header information is assembled based upon the comparison results. The data packets have their headers replaced by the new header information on the fly before being sent to their destinations, or the new header information may be dropped if certain conditions are met.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: October 21, 2008
    Assignee: RETI Corporation
    Inventors: Kuen-Rong Hsieh, Lan-feng Wang, Chiu-tien Wu
  • Patent number: 7430207
    Abstract: The present invention is to disclose a scheduler which comprising a priority tagging module for receiving a plurality of information chucks, a plurality of output lines, and a WRR (weighted round robin) module. In this regards, each information chucks are tagged with a priority tag by said priority tagging module according to a priority classification scheme. In addition, the WRR module further comprises a bucket list, which has a plurality of buckets, and a control module. Each bucket stores a ticket, which comprises an identification representing one of the plurality of output lines and an associated weight value of the represented output line. Besides, the control module receives the tagged information chucks from the priority tagging module and schedules the tagged information chucks into the plurality of output lines according to a scheduling scheme based on said bucket list.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: September 30, 2008
    Assignee: Reti Corporation
    Inventors: Chiutien Wu, Lan-Feng Wang
  • Publication number: 20060203721
    Abstract: A system and method for forwarding data packets with quality of service and rate control. A plurality of data packets are received from a plurality of sources. The header information of each data packet is extracted and compared against a plurality of tables, and then new header information is assembled based upon the comparison results. The data packets have their headers replaced by the new header information on the fly before being sent to their destinations, or the new header information may be dropped if certain conditions are met.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 14, 2006
    Inventors: Kuen-Rong Hsieh, Lan-feng Wang, Chiu-tien Wu
  • Publication number: 20060176807
    Abstract: The present invention is to disclose a scheduler which comprising a priority tagging module for receiving a plurality of information chucks, a plurality of output lines, and a WRR (weighted round robin) module. In this regards, each information chucks are tagged with a priority tag by said priority tagging module according to a priority classification scheme. In addition, the WRR module further comprises a bucket list, which has a plurality of buckets, and a control module. Each bucket stores a ticket, which comprises an identification representing one of the plurality of output lines and an associated weight value of the represented output line. Besides, the control module receives the tagged information chucks from the priority tagging module and schedules the tagged information chucks into the plurality of output lines according to a scheduling scheme based on said bucket list.
    Type: Application
    Filed: April 19, 2005
    Publication date: August 10, 2006
    Inventors: Chiutien Wu, Lan-Feng Wang