Abstract: A processing circuit is provided. The processing circuit includes an image-providing device, an adjustment device, a resistive memory, and a control circuit. The image-providing device is configured to provide a target image. The adjustment device adjusts the scale of a template image to generate a sample image according to the setting information. The resistive memory includes a storage region and a computation circuit. The storage region stores the target image. The computation circuit computes the sample image and the target image to generate a plurality of computation results. The control circuit finds a matching position that matches the sample image in the target image according to the computation results.

Abstract: A method for updating firmware is provided. The method includes dividing the firmware into a plurality of sections, and assigning the sections to a plurality of block segments. The method includes generating a firmware chain by generating a series of blocks corresponding to the block segments and creating links between the blocks, and publishing the block segments onto the firmware chain. The method includes obtaining the sections from the firmware chain, and updating the sections to a first storage bank of the target device.

Abstract: A control device includes a first memory, a second memory, a processing circuit and an input-output interface. The first memory stores a secure-bootloader program code. The second memory stores a first specific program code. The processing circuit performs the secure-bootloader program code to execute a first legality verification on the first specific program code. When the first specific program code passes the first legality verification, the processing circuit performs the first specific program code to generate a verification signal. The input-output interface is configured to output the verification signal to an external device and receives a response signal from the external device. The processing circuit executes a second legality verification on the reply signal. When the reply signal does not pass the second legality check, the processing circuit ignores a request from the external device.

Abstract: A control chip coupled to a sensing circuit and including a first memory, an accessing circuit, a second memory, and a processing circuit is provided. The first memory includes a first storage area and a second storage area. The first storage area stores sensing data provided by the sensing circuit. The second storage area stores processing parameters. The accessing circuit reads continuous data of the first storage area according to a first access command to generate first read data and reads at least one processing parameter of the second storage area according to a second access command to generate second read data. The second memory stores the first and second read data. The processing circuit reads the second memory and processes the first read data according to the second read data to generate first processed data. The processing circuit stores the first processed data in the second memory.

Abstract: A microcontroller circuit is provided. The microcontroller circuit includes a memory, a check module, and a processor. The memory includes a main memory block and a backup memory block. The main memory block has a boot setting and the backup memory block has a backup boot setting. The check module includes a register. The processor is configured to determine whether the backup memory block of the memory has been backed up according to the register of the check module in response to a boot signal, and to compare the boot setting with the backup boot setting when the backup memory block of the memory has been backed up. When the boot setting is different from the backup boot setting, the processor is configured to perform a boot initialization procedure according to the backup boot setting.

Abstract: A micro-controller circuit including a sensor circuit, a processing circuit, a storage circuit, and an adjustment circuit is provided. The sensor circuit senses a physical parameter to generate sense information. The processing circuit performs an operation on the sense information to generate a processed signal. The storage circuit stores the processed signal and predetermined information. The adjustment circuit utilizes a machine learning method to process the processed signal stored in the storage circuit to generate a learning result. In response to the learning result not matching the predetermined information, the adjustment circuit adjusts the predetermined information.

Abstract: A control chip coupled to a central processing unit (CPU) and including a selection circuit, a buffer circuit, a calculation circuit, and a motion judgment circuit is provided. The selection circuit selects some of the first image macro-blocks of a first image frame and some of the second image macro-blocks of a second image frame. The buffer circuit stores the selected first and second image macro-blocks. The calculation circuit accesses the buffer circuit and calculates the differences between the selected first and second image macro-blocks to generate a calculated result. The motion judgment circuit determines whether the first and second image frames are the same according to the calculated result. In response to the second image frame not being the same as the first image frame, the motion judgment circuit wakes up the CPU so that the CPU enters a normal mode from a low-power mode.

Abstract: A motion-detection system including a camera and a storage device is provided. The camera captures a color image and transmits the color image to a pre-processor. In a low-power mode, the pre-processor retrieves the luminance value of each pixel in the color image to generate a luminance image and performs resolution reduction on the luminance image to generate an input image. The motion-identifying device identifies a motion-object block within the input image and calculates the amount of movement of the motion-object block. When the amount of movement reaches an identification threshold, the motion-detection system enters a normal mode from the low-power mode. In the normal mode, when an object-identifying model determines that an object in the motion-object block is not a predefined object, the motion-detection system enters the low-power mode.

Abstract: A microphone array includes a four-channel serial peripheral interface, a core logic unit, a data receiving unit and a voice recognition unit. The four-channel serial peripheral interface includes a bit clock signal line, a frame clock signal line, and four data signal lines, the core logic unit includes a frequency divider module for converting the control signal and the clock signal to provide a bit clock signal and a frame clock signal. The data receiving unit includes a shift register and a buffer, the shift register is connected to four data signal lines and receives input data of the four digital microphones, and the buffer is connected to the shift register. The voice recognition unit is connected to the data receiving unit and receives microphone signals of the four digital microphones to perform voice recognition.

Abstract: An Over-the-Air (OTA) method includes controlling the current state using a control state register. The method includes recording the current state and the hash algorithm. A sorting setter obtains a random number from a server. The method includes sorting the random numbers according to a preset sorting method to obtain a sorting parameter. A hash calculator uses the sorting parameter as the input of the hash algorithm. The hash algorithm outputs a device-side hash result and transmits the device-side hash result to the server through a transmission device. After the server receives the device-side hash result, it compares the device-side hash result with the server-side hash result calculated by the server.

Abstract: An electronic device including a power supply device and a load is provided. The power supply device includes an energy harvest circuit, a power management circuit, and an energy storage element. The energy harvest circuit receives a wireless signal and harvests energy from the wireless signal to generate a first output voltage. The power management circuit processes the first output voltage to generate a second output voltage. The energy storage element is charged by the second output voltage to provide an operation voltage. The load operates according to the operation voltage.

Abstract: A method for updating firmware is provided. The method includes dividing the firmware into a plurality of sections, and assigning the sections to a plurality of block segments. The method includes generating a firmware chain by generating a series of blocks corresponding to the block segments and creating links between the blocks, and publishing the block segments onto the firmware chain. The method includes obtaining the sections from the firmware chain, and updating the sections to a first storage bank of the target device.

Abstract: An image binarization method and an electronic device using the same are provided. The method includes capturing an image by an image capturing device; selecting a target pixel row arranged at the front from one or more unselected first pixel rows among M pixel rows of the image according to a row order by a binarization circuit; performing, by the binarization circuit, a binarization operation on the target pixel row to obtain a binarized pixel row; storing the binarized pixel row to a main memory by the binarization circuit; performing, by the binarization circuit, the binarization operation to the remaining one or more first pixel rows until M binarized pixel rows are obtained, so as to complete the binarization operation.

Abstract: A microphone array includes a four-channel serial peripheral interface, a core logic unit, a data receiving unit and a voice recognition unit. The four-channel serial peripheral interface includes a bit clock signal line, a frame clock signal line, and four data signal lines, the core logic unit includes a frequency divider module for converting the control signal and the clock signal to provide a bit clock signal and a frame clock signal. The data receiving unit includes a shift register and a buffer, the shift register is connected to four data signal lines and receives input data of the four digital microphones, and the buffer is connected to the shift register. The voice recognition unit is connected to the data receiving unit and receives microphone signals of the four digital microphones to perform voice recognition.

Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.

Abstract: An electronic processing device including a memory and a Micro Control Unit (MCU) is provided. The memory includes a first memory block and a second memory block. The MCU executes first program code stored in the first memory block to write an update program code into the second memory block, and remaps a base address for a reboot of the electronic processing device from the first memory block to the second memory block in response to successfully writing the update program code into the second memory block. After that, the MCU triggers the reboot of the electronic processing device to execute the update program code stored in the second memory block.

Abstract: A recognition method includes: receiving a training voice or a training image; and extracting a plurality of voice features in the training voice, or extracting a plurality of image features in the training image; wherein when extracting the voice features, a specific number of voice parameters are generated according to the voice features, and the voice parameters are input into a deep neural network (DNN) to generate a recognition model. When extracting the image features, the specific number of image parameters are generated according to the image features, and the image parameters are input into the deep neural network to generate the recognition model.

Abstract: An image binarization method and an electronic device using the same are provided. The method includes capturing an image by an image capturing device; selecting a target pixel row arranged at the front from one or more unselected first pixel rows among M pixel rows of the image according to a row order by a binarization circuit; performing, by the binarization circuit, a binarization operation on the target pixel row to obtain a binarized pixel row; storing the binarized pixel row to a main memory by the binarization circuit; performing, by the binarization circuit, the binarization operation to the remaining one or more first pixel rows until M binarized pixel rows are obtained, so as to complete the binarization operation.

Abstract: An electronic processing device including a memory and a Micro Control Unit (MCU) is provided. The memory includes a first memory block and a second memory block. The MCU executes first program code stored in the first memory block to write an update program code into the second memory block, and remaps a base address for a reboot of the electronic processing device from the first memory block to the second memory block in response to successfully writing the update program code into the second memory block. After that, the MCU triggers the reboot of the electronic processing device to execute the update program code stored in the second memory block.

Abstract: A storage device, which is coupled to a host and a first register, includes a first mapping register, a shadow register, and a controller. The first mapping register is configured to store the first address of the first register. The shadow register includes a first shadow section mapped to a register section of the first register. The controller receives an initialization instruction generated by the host to write the first address into the first mapping register so that the first shadow section is mapped to the first register section.