Abstract: A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: A sector erase method for use in a non-volatile memory, such as a FLASH memory, including a plurality of memory cells in rows and columns, the memory cells being divided into a plurality of sectors. The sector erase method includes erasing the memory cells of a first sector by applying successive erase pulses that increase in voltage magnitude or pulse width, until erasure of the first sector is verified. Erase condition information corresponding to the first sector, is recorded, this information including a number of times successive erase pulses are needed to be applied in order to erase the memory cells of the first sector. Memory cells of a next sector are erased by applying a first erase pulse having a voltage magnitude or pulse width determined from the recorded erase condition information. The first erase pulse may be incremented if the first erase pulse fails to erase that next sector.

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.

Abstract: A sector erase method for use in a non-volatile memory, such as a FLASH memory, including a plurality of memory cells in rows and columns, the memory cells being divided into a plurality of sectors. The sector erase method includes erasing the memory cells of a first sector by applying successive erase pulses that increase in voltage magnitude or pulse width, until erasure of the first sector is verified. Erase condition information corresponding to the first sector, is recorded, this information including a number of times successive erase pulses are needed to be applied in order to erase the memory cells of the first sector. Memory cells of a next sector are erased by applying a first erase pulse having a voltage magnitude or pulse width determined from the recorded erase condition information. The first erase pulse may be incremented if the first erase pulse fails to erase that next sector.

Abstract: A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.

Abstract: A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.

Abstract: A method for forming a non-volatile memory cell includes depositing an oxide layer over a component stack including a dielectric layer over a first conductive layer. A portion of an upper section of the oxide layer is removed such that the dielectric layer is exposed. The dielectric layer and a remainder of the oxide layer upper section are removed such that upper surfaces of the oxide layer and the first conductive layer are substantially planar. A second conductive layer is formed over the upper surfaces of the first conductive layer and the oxide layer. A non-volatile memory array is formed including multiple spaced and parallel bit lines in a substrate surface. Multiple stacked layers, including an electron trapping layer, are on the substrate surface over the bit lines. Multiple spaced word lines are over the stacked layers. The word lines are parallel to one another and perpendicular to the bit lines.

Abstract: A word line strap layout structure is described, comprising an isolation post, a word line, a contact and a metal line. The isolation post is located on a substrate between two memory areas. The word line crosses over the substrate and the isolation post, and the contact is located on the word line over the isolation post, wherein the isolation post and the contact are of the same scale in size. The metal line is located over the substrate electrically connecting with the word line via the contact.

Abstract: A word line strap layout structure is described, comprising an isolation post, a word line, a contact and a metal line. The isolation post is located on a substrate between two memory areas. The word line crosses over the substrate and the isolation post, and the contact is located on the word line over the isolation post, wherein the isolation post and the contact are of the same scale in size. The metal line is located over the substrate electrically connecting with the word line via the contact.

Abstract: A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.