Abstract: The present invention provides a “living” radical polymerization method for a vinyl monomer by near-infrared photothermal conversion. The method comprises irradiating a reactor with near-infrared light of 750-850 nm, wherein the reactor has a first chamber and a second chamber that are isolated from each other, the first chamber contains an organic solution of a near-infrared light responsive croconaine dye, and the second chamber is provided with a closed reaction flask containing a reaction solution, the reaction solution comprises a vinyl monomer, two or more of an ATRP initiator, an ATRP ligand, an ATRP catalyst, an RAFT reagent, a thermal initiator, and an additive, and an organic solvent; and the near-infrared light responsive dye converts the near-infrared light into heat energy, by which the reactor is heated to 50-100° C. to polymerize the monomer in the reaction solution, to obtain polymers with controlled molecular weights and molecular weight distributions.

Abstract: Disclosed are a cranial CT-based grading method and a corresponding system, which relate to the field of medical imaging. The cranial CT-based grading method as disclosed solves the problems of relatively great subjective disparities and poor operability in eye-balling ASPECTS assessment. The grading method includes: determining frames where target image slices are located from to-be-processed multi-frame cranial CT data; extracting target areas; performing infarct judgment on each target area included in the target areas to output an infarct judgment outcome regarding the target area; and outputting a grading outcome based on infarct judgment outcomes regarding all target areas.

Abstract: This disclosure provides a semiconductor device, a method of manufacturing the same, a 3D NAND memory, and a memory system. The semiconductor device includes a substrate having a first trench at a surface thereof, and a first insulating layer formed on the surface of the substrate and inside the first trench. The first insulating layer formed inside the first trench forms a second trench that is embedded in the first trench. The semiconductor device further includes a conducting layer formed on a surface of the first insulating layer away from the substrate and inside the second trench.

Abstract: A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.

Abstract: The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: The present disclosure discloses a semiconductor device, a three-dimensional memory and a method for fabricating the semiconductor device. The method includes forming a shallow trench isolation trench in a substrate. The substrate comprises an active region including a source region, a channel region, and a drain region. The shallow trench isolation trench is located on a periphery of the active region of the substrate. The method further comprises forming a bottom isolating layer in a bottom portion of the shallow trench isolation trench, forming a gate structure on a channel region of the substrate, and forming a hard insulating layer in an upper portion of the shallow trench isolation trench and on sidewalls of the active region, such that the hard insulating layer covers a source region and a drain region of the substrate.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: The disclosure provides a semiconductor device and a method for fabricating the same, a three-dimensional memory apparatus and a memory system. The semiconductor device includes: a substrate including a first region and a second region, the first region being formed with a recess; a first shallow trench isolation structure and a second shallow trench isolation structure located in the first region and the second region respectively; and a first gate oxide layer on the recess and a second gate oxide layer in the second region and on the second shallow trench isolation structure.

Abstract: The present disclosure discloses a semiconductor device and a fabrication method thereof. In the method, firstly etching a substrate in a first device region to form at least one first trench and then etching the substrate in both first device region and second device region to form at least one first isolation trench at the positions corresponding to the at least one first trench and form at least one second isolation trench in the second device region. Herein a depth of the first isolation trench is larger than that of the second isolation trench.

Abstract: A semiconductor device, a manufacturing method thereof and a NAND memory device are disclosed. The method comprises forming a substrate including an active region and an isolation region located around the active region. The active region includes a source region, a channel region, and a drain region. The method further comprises forming a groove between the isolation region and the channel region and partially above the isolation region, and forming a gate in the groove and on the channel region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a transistor in active area. The active area is in a substrate and comprises a recess, a surface of the recess having an offset from a surface of the substrate. The transistor comprises a gate electrode, the gate electrode comprising a first portion in the recess and a second portion outside the recess.

Abstract: A semiconductor structure, fabrication method and three-dimensional memory are disclosed. A method of fabricating a semiconductor structure includes providing a substrate including a first device region and a second device region; forming a plurality of first recesses in the first device region and a second recess in the second device region, the first recesses and the second recess being formed simultaneously; forming a first isolation trench in the first device region; and forming a second isolation trench in the second device region at a position of the second recess.

Abstract: A semiconductor device and a method for manufacturing the same, and a NAND memory device are disclosed. The method comprises: forming a substrate that comprises a first active region and an isolation region; forming a first groove between the isolation region and the first channel region, the first groove being partially located in the isolation region, and not penetrating through the isolation region; forming a first gate insulating layer covering the first groove and the first channel region; forming a first gate on the first gate insulating layer, the first gate covering the first channel region and filling the first groove.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. A substrate including a first device region and a second device region is provided. A first isolation structure is formed in the substrate of the first device region and a second isolation structure is formed in the substrate of the second device region. Ion implantation on the first isolation structure is performed. The first isolation structure and the second isolation structure are etched back to form a first recess in the first isolation structure and a second recess in the second isolation structure.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The method includes: forming a first bottom isolation layer and a second bottom isolation layer in a substrate, the thickness of the second bottom isolation layer being less than that of the first bottom isolation layer; and forming, on the a first active area in the substrate, a first gate structure extending to the first bottom isolation layer and forming, on a second active area in the substrate, a second gate structure extending to the second bottom isolation layer.

Abstract: Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. A vertical structure is formed penetrating the alternating dielectric stack in a vertical direction. A bottom dielectric layer of the alternating dielectric stack is removed. An epitaxial layer is formed between the substrate and the alternating dielectric stack after removing the bottom dielectric layer. An insulating layer is formed on the epitaxial layer. The insulating layer is located between the epitaxial layer and the alternating dielectric stack. The influence of the step of forming the vertical structure on the epitaxial layer may be avoided, and defects at the interface between the epitaxial layer and the bottom dielectric layer may be avoided accordingly.

Abstract: The present invention provides a “living” radical polymerization method for a vinyl monomer by near-infrared photothermal conversion. The method comprises irradiating a reactor with near-infrared light of 750-850 nm, wherein the reactor has a first chamber and a second chamber that are isolated from each other, the first chamber contains an organic solution of a near-infrared light responsive croconaine dye, and the second chamber is provided with a closed reaction flask containing a reaction solution, the reaction solution comprises a vinyl monomer, two or more of an ATRP initiator, an ATRP ligand, an ATRP catalyst, an RAFT reagent, a thermal initiator, and an additive, and an organic solvent; and the near-infrared light responsive dye converts the near-infrared light into heat energy, by which the reactor is heated to 50-100° C. to polymerize the monomer in the reaction solution, to obtain polymers with controlled molecular weights and molecular weight distributions.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.