Abstract: A system and method for generating 2.sup.n test patterns is disclosed. The system utilizes a linear feedback shift register (LFSR) to generate a sequence of 2.sup.n -1 test patterns. In addition, the system includes apparatus external to the shift register which generates a 2.sup.n th test pattern. A switching circuit is employed to insert the 2.sup.n th test pattern into the sequence of test patterns. Therefore, a 2.sup.n test pattern sequence is generated. The test pattern sequence produced is pseudo-random in nature. The system further includes an output for providing a test pattern; such output could be used for the testing of a very large scale integration (VSLI) sub-system such as read only memory (ROM). A method utilizing the techniques embodied in the system is also disclosed.