Abstract: A method for optical proximity correction of a design of a pattern on a surface is disclosed with the method comprising the steps of inputting desired patterns for the substrate and inputting a set of characters some of which are complex characters that may be used for forming the patterns on the surface. A method of creating glyphs is also disclosed.

Abstract: A method for optical proximity correction (OPC) of a desired pattern for a substrate is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form on a surface an OPC-corrected version of the desired substrate pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the OPC-corrected version of the desired pattern for the substrate. In some embodiments, optimization may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots, that is, glyphs. A method for creating glyphs is also disclosed, in which patterns that would result on a surface from one or a group of VSB shots are pre-calculated.

Abstract: A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots.

Abstract: A method for fracturing or mask data preparation or proximity effect correction is disclosed which comprises the steps of inputting patterns to be formed on a surface, a subset of the patterns being slightly different variations of each other and selecting a set of characters some of which are complex characters to be used to form the number of patterns, and reducing shot count or total write time by use of a character varying technique. A system for fracturing or mask data preparation or proximity effect correction is also disclosed.

Abstract: A method for manufacturing a surface, the surface having a multiplicity of slightly different patterns, is disclosed with the method comprising the steps of designing a stencil mask having a set of characters for forming the patterns on the surface and reducing shot count or total write time by use of a character varying technique. A system for manufacturing a surface is also disclosed.

Abstract: Computer-implemented methods for detecting defects in reticle design data are provided. One method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. The method further includes detecting defects in the reticle design data using the second simulated images. Another method includes the generating steps described above in addition to determining a rate of change in a characteristic of the second simulated images as a function of the different values. This method also includes detecting defects in the reticle design data based on the rate of change.

Abstract: Computer-implemented methods for detecting defects in reticle design data are provided. One method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. The method further includes detecting defects in the reticle design data using the second simulated images. Another method includes the generating steps described above in addition to determining a rate of change in a characteristic of the second simulated images as a function of the different values. This method also includes detecting defects in the reticle design data based on the rate of change.

Abstract: Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

Abstract: A method of inspecting a reticle for defining a circuit layer pattern. First, the circuit layer pattern is analyzed to obtain a circuit characterization, and then, an area of the reticle is categorized into a first region and a second region based on the circuit characterization. A test reticle image of the reticle and a baseline representation containing an expected pattern of the test reticle image are provided. The first region of the test reticle image is compared to the first region of the baseline representation by a first analysis, and the second region of the test reticle image is compared to the second region of the baseline representation by a second analysis. The first analysis differs from the second analysis and this difference is based on difference in the circuit characterization of the first and second regions.

Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

Abstract: Disclosed is a method of inspecting a reticle for defects that occur over time. The invention accomplishes this by generating and storing a “baseline” image of the reticle and then periodically generating a “current” image of the reticle and comparing the current and baseline images. The baseline image is taken at a time when the reticle is known to be acceptable. This may be when the reticle has been “qualified” by an optical test or when a die fabricated by reticle has passed an electrical test. Also disclosed in a method for compacting the baseline image before storage.

Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.

Abstract: A memory apparatus for storage and retrieval of digital data is disclosed, including a controller and a memory element having an array of memory cells, each cell having fewer ports than are provided by the memory system. The memory cells are adapted for storing digital data words, each word being a set of bits or symbols. The memory array is partitioned into a plurality of bins for storing words, the individual bits of each word being distributed in a selected addressing sequence among a plurality of selected bins in the memory array, such that bin reading conflicts generate a number of errors less than or equal to a numerical error limit K, where K is less than the number of bits in a word. The data words can be manipulated so as to produce error-free results.

Abstract: An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

Abstract: Apparatus is disclosed for reversing the bit order of a portion of a digital word. The apparatus contains a shifter, connected to the input through a bit reversing means, and selector means which forms an output word by selecting appropriate bits either directly from the input word or from the output of the shifter.

Abstract: In the apparatus disclosed herein, a data signal to be phase adjusted is applied to a plurality of delay lines providing progressively greater delays. The outputs of the several delay lines are compared over a period of time and a selection of one of the output signals for utilization is made based on choosing that delay line output which is in opposition to that pair of outputs which straddles or encompasses the most transitions.

Abstract: A programmable non-volatile memory cell is disclosed that can be written into the "1," "0," or "previous" state in the presence of unfocused illumination, preferrably ultraviolet (UV) light. The programmed state is controlled by low electrical voltages. Once the illumination is removed the programmed state is non-volatile. The memory cell can be fabricated using conventional MOS processing techniques with no additional mask steps. The cell can thus be implemented on virtually all silicon gate nMOS and CMOS processes.

Abstract: A semiconductor diode laser system with microwave mode locking. The system includes a semiconductor laser diode and an external reflector positioned to receive radiation that emits from the diode and reflects the same back into the diode, the microwave mode locking serving to modulate the radiation and the external reflector being properly positioned to return the radiation to the diode at a return time equal to the period of the drive signal or a submultiple thereof.

Abstract: Heat exchange apparatus for improving the efficiency of a fireplace is disclosed in the form of a plurality of heat transfer conduits connected at one end to a manifold and containing a plurality of heat exchange elements. A fan means directs air through the manifold and then through the conduits for contact with the heat exchange elements to thereby heat the air which is then discharged into a room.