Abstract: A method and apparatus for synchronizing load operations. In one embodiment, an apparatus includes a decode circuit to decode a load fence instruction. An execution unit executes the load fence instruction after it has been decoded by the decode circuit.

Abstract: A method and apparatus for synchronizing load operations. In one embodiment, an apparatus includes a decode circuit to decode a load fence instruction. An execution unit executes the load fence instruction after it has been decoded by the decode circuit.

Abstract: A system and a method of sorting performance data for one or more system configurations are provided. Performance data on multiple programs that run on at least one system is obtained. The performance data includes a profile for each program obtained from a tool. The performance data for each profile is automatically sorted to allow for comparison between the profiles.

Abstract: A method and apparatus for synchronizing load operations. In one embodiment, an apparatus includes a decode circuit to decode a load fence instruction. An execution unit executes the load fence instruction after it has been decoded by the decode circuit.

Abstract: A method and apparatus for accessing pages in physical memory, where the physical memory is described. The present invention provides a paged memory system having multiple page sizes. Pages of a first size are accessed via a page directory entry and a corresponding page table entry. The page directory entry stores a base physical address for a corresponding page table and control bits indicating permissions. The page table entry stores a base physical address of the page in memory. In one embodiment, the page table entry inherits permissions from the page directory entry. Pages of a second size are accessed via a page directory entry that stores a base physical address of the page and control bits indicating permissions associated with the page. In another embodiment, entries to the page directory table and the page table are 4-bytes in size and provide paging for memory up to 1.1 Terabytes in size.

Abstract: The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.