Abstract: An apparatus includes: a media; a head over the media; a head actuation motor (HAM) coupled to the head; control circuitry, coupled to the head actuation motor, including: a system-on-chip (SOC) configured to manage a control of the head actuation motor, a pulse width modulation (PWM) code bus, coupled to the SOC, configured to communicate the control of the HAM, and a power integrated circuit (PIC), coupled to the PWM code bus, configured to drive a HAM control signal.

Abstract: Systems and methods are provided for efficiently powering down elements and buses of a system without negatively impacting traffic. A power manager receives information from subsystems and determines whether a particular subsystem or bus can be powered down. The power manager sends a message to a subsystem when the subsystem or bus can be safely powered down. Blocker modules are coupled to buses, and the blocker modules respond with an error message if a subsystem attempts to send data over an inactive bus.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: A method to combine trace data for multiple systems within an embedded system is provided. This method involves coupling a set of trace sources within the embedded system to a trace system. A subset of trace source(s) may then be selected from the set of trace sources. The subset of trace sources may be formatted to produce a packetized trace stream. The packetized trace stream may then be provided to external interface circuitry. External circuitry coupled to the trace system allows for analysis of the packetized trace streams regarding internal operations within the embedded system. An arbitrator may determine which trace source(s) from the set of trace sources are selected to be within the subset of trace sources. The arbitrator may use several criteria to make this determination.

Abstract: Methods and structures for providing patches or updates to embedded ROM firmware simply and inexpensively while avoiding imposition of execution or memory fetch overhead. A patch memory includes locations storing addresses and optional alternate data values. Read/fetch operations addressed to a firmware ROM memory are applied in parallel to the patch memory. All locations of the patch memory may be compared in parallel to the supplied address to determine if a match is found in patch memory. If no match is found, the read/fetch memory cycle completes normally retrieving data from the ROM memory. If a match is found, the alternate data value is applied to the data bus in place of the ROM memory data retrieved. Any ROM location may therefore be patched regardless of whether the location stores instruction or data.

Abstract: A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

Abstract: A method to combine trace data for multiple systems within an embedded system is provided. This method involves coupling a set of trace sources within the embedded system to a trace system. A subset of trace source(s) may then be selected from the set of trace sources. The subset of trace sources may be formatted to produce a packetized trace stream. The packetized trace stream may then be provided to external interface circuitry. External circuitry coupled to the trace system allows for analysis of the packetized trace streams regarding internal operations within the embedded system. An arbitrator may determine which trace source(s) from the set of trace sources are selected to be within the subset of trace sources. The arbitrator may use several criteria to make this determination.

Abstract: A data scrambling circuit is provided. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.

Abstract: A method to combine trace data for multiple systems within an embedded system is provided. This method involves coupling a set of trace sources within the embedded system to a trace system. A subset of trace source(s) may then be selected from the set of trace sources. The subset of trace sources may be formatted to produce a packetized trace stream. The packetized trace stream may then be provided to external interface circuitry. External circuitry coupled to the trace system allows for analysis of the packetized trace streams regarding internal operations within the embedded system. An arbitrator may determine which trace source(s) from the set of trace sources are selected to be within the subset of trace sources. The arbitrator may use several criteria to make this determination.

Abstract: Methods and structures for an improved processor pipeline to eliminate the effect of correctable soft errors on processor/memory pipeline performance. Features and aspects hereof provide that the pipeline is extended by the addition of one or more information correction stages to correct a soft error using the fetched unit of information and the associated error correcting codes. By extending the pipeline, soft error correction does not stall the pipeline and hence system performance is improved in the face of soft errors from an error correcting memory subsystem.

Abstract: Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.

Abstract: Herein described are at least a method and a system for prioritizing the transmission of one or more types of signals through a serial port. Various aspects of the present invention may be implemented using a serial port interface module that facilitates communication between any two devices. In a representative embodiment, the two devices comprise a disk drive controller and a disk drive motor controller used in a hard disk drive. In a representative embodiment, the method and the system are used in the hard disk drive for prioritizing the transmission of multirate voice coil motor (VCM) updates and other asynchronous data signals between the disk drive controller and disk drive motor controller through the serial port.

Abstract: Hard disk drive progressive channel interface. A novel approach is presented by which the interface between a channel circuitry and a controller circuitry, such as those which can be implemented within a hard disk drive (HDD). Because of the location in which the disk management operations are supported and performed within the channel circuitry, the interface between the channel circuitry and the controller circuitry can be implemented to support direct memory access (DMA) protocol data transfers and control there between. Because the disk management operations are supported within the channel circuitry, as opposed to the controller circuitry, then the disk management operations need not necessarily comply with an interface between the channel circuitry and the controller circuitry. This allows for better control of the disk management operations as well as a much broader range and type of interface that can be employed for the interface between the two circuitries.

Abstract: A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

Abstract: Herein described is at least a method and system for improving the performance of a disk drive. A cache work queue and a disk work queue operate together as a dual work queue to facilitate efficient processing of one or more read/write operations performed by the disk drive. In a representative embodiment, the disk drive controller comprises a host interface, a cache buffer, and a disk drive media interface. The disk drive controller comprises the necessary circuitry to execute one or more host commands provided by a host computer. Further, the disk drive controller may facilitate the generation of the cache work queue and the disk work queue. The disk drive controller executes one or more host commands that are received through the host interface such that the cache work queue and disk work queue are employed when a read or write operation is performed.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area of the cache. In another embodiment, the invention prevents reading previous line data for a new tag from main memory when the new tag represents a currently unused area of the cache.