Patents by Inventor Lance Hehenberger

Lance Hehenberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for verifying out-of-order page fault detection
    Patent number: 10936505
    Abstract: Verification of asynchronous page fault in a simulated environment. The methods include providing a simulated environment that includes a simulated processor core, a memory, and an interrupt handler. The methods also include executing a test code in the simulated environment by: executing a non-irritator thread code comprising a plurality of load instructions that span at least two slices of the simulated processor core, executing a first irritator thread code to bias against the execution of the plurality of load instruction by one of the at least two slices of the simulated processor core, and executing a second irritator thread code to invalidate caching of page table entries during execution of the plurality of load instructions in a fast access cache memory.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: John M. Ludden, David Campbell, Lance Hehenberger, Madhusudan Kadiyala, George W. Rohrbaugh, III
  • METHODS AND SYSTEMS FOR VERIFYING OUT-OF-ORDER PAGE FAULT DETECTION
    Publication number: 20200201778
    Abstract: Verification of asynchronous page fault in a simulated environment. The methods include providing a simulated environment that includes a simulated processor core, a memory, and an interrupt handler. The methods also include executing a test code in the simulated environment by: executing a non-irritator thread code comprising a plurality of load instructions that span at least two slices of the simulated processor core, executing a first irritator thread code to bias against the execution of the plurality of load instruction by one of the at least two slices of the simulated processor core, and executing a second irritator thread code to invalidate caching of page table entries during execution of the plurality of load instructions in a fast access cache memory.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: John M. Ludden, David Campbell, Lance Hehenberger, Madhusudan Kadiyala, George W. Rohrbaugh, III
  • Methods and apparatus for transferring data
    Publication number: 20060222004
    Abstract: In a first aspect, a first method is provided for transferring data using an Infiniband (IB) protocol. The first method includes the steps of (1) receiving a non-IB packet having header data and payload data at a first node of a computer system; and (2) modifying data in the non-IB packet to convert the non-IB packet to an IB packet having header data and payload data. The header data of the non-IB packet is not included in the payload data of the IB packet resulting from the conversion. Numerous other aspects are provided.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 5, 2006
    Applicant: International Business Machines Corporation
    Inventors: Bruce Beukema, Lance Hehenberger, Nathaniel Sellin, Robert Shearer, Bruce Walk