Abstract: A cache system and a method for an extent-based cache memory design are disclosed. The method Includes providing a storage device and a host device where each device is in communication with the memory and creating an extent record associated with the memory. A storage device access request is received from the host device and at least one state field value in the extent record is changed in response to the access request from the host device. The size of an extent associated with the extent record and allocated within the memory may be based on the access request and any additional speculative data. The at least one state field value may be selected from the group consisting of extent size, valid count, hit count, and dirty count. The storage device may be implemented as an intelligent hard disk drive and the memory may be implemented by random access memory (RAM).

Abstract: A pipelined arithmetic processor includes a pair of multipliers in parallel feeding an ALU that, in turn, feeds a pair of parallel accumulators, the various sections being connected by controllable data paths and controlled by a set of pipelined registers feeding a series of decoders.