Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in memory. The process executes the software that implements the first and second algorithms.

Abstract: Herein described are at least a method and a system for prioritizing the transmission of one or more types of signals through a serial port. Various aspects of the present invention may be implemented using a serial port interface module that facilitates communication between any two devices. In a representative embodiment, the two devices comprise a disk drive controller and a disk drive motor controller used in a hard disk drive. In a representative embodiment, the method and the system are used in the hard disk drive for prioritizing the transmission of multirate voice coil motor (VCM) updates and other asynchronous data signals between the disk drive controller and disk drive motor controller through the serial port.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: Herein described is at least a method and system for improving the performance of a disk drive. A cache work queue and a disk work queue operate together as a dual work queue to facilitate efficient processing of one or more read/write operations performed by the disk drive. In a representative embodiment, the disk drive controller comprises a host interface, a cache buffer, and a disk drive media interface. The disk drive controller comprises the necessary circuitry to execute one or more host commands provided by a host computer. Further, the disk drive controller may facilitate the generation of the cache work queue and the disk work queue. The disk drive controller executes one or more host commands that are received through the host interface such that the cache work queue and disk work queue are employed when a read or write operation is performed.

Abstract: A digital data separator that is capable of separating data signals and clock signals from an encoded data stream. The digital data separator includes a synchronizer to synchronize the encoded data stream with the system clock of the digital data separator. An up-counter counts the number of clock pulses between valid logic 1's in the encoded digital data stream. Combination logic compares the value of the up-counter with established threshold values to determine whether the data separator has received a valid logic 1. The combinatorial logic also reset the up-counter on determining that a valid logic 1 was received.

Abstract: A cache system and method for configuring and accessing a cache that enables a binary-sized memory space to be efficiently shared amongst cache and non-cache uses. A storage device is provided having a plurality of blocks where each block is identified with a block address. An access request identifies a target block address. The target block address includes an upper portion and a lower portion. A non-binary divide is performed on the upper portion to produce a quotient and a remainder. The remainder portion is combined with the lower portion to create an index. The index is applied to a tag memory structure to select an entry or set of entries in the tag memory structure. The content of the selected entry is compared to the quotient portion to determine if the target block is represented in the cache.

Abstract: A gated scan flop circuit and methods of making the gated scan flop circuit are provided. In one example, the scan flop circuit includes a sub-scan flop circuit that incorporates a multiplexer and a flip flop circuit, and a data terminal D that is connected to the sub-scan flop circuit. Also provided is a first logic gate that is configured to receive a scan input terminal SI and a clock gate terminal G. The first logic gate has a first logic gate output that is connected to the sub-scan flop circuit. A scan enable terminal SE is connected to the sub-scan flip circuit, and a latch circuit is configured to receive the clock gate terminal G, and track its input while the clock terminal CLK is inactive. A second logic gate having a second logic gate output is provided that is configured to receive as inputs the scan enable terminal SE and the latched clock gate terminal G. A third logic gate is configured to receive a clock terminal CLK and the second logic gate output.

Abstract: A method comprises receiving a diskette into a drive, determining the logical format type of the data written on the diskette, and targeting any recorded track on either surface of the diskette that has both inner and outer adjacent tracks. The head actuator in the drive is moved to the expected position for the targeted track that has been determined by a factory precalibration. The head actuator is then stepped inside by one sixteenth of the width of a standard track pitch and an attempt is made to read a sector header from the recorded track. If the reading of the sector header succeeded, the head actuator is stepped in again by one sixteenth and the sector header is read again. Such inward stepping is continued until the reading of the sector header fails. The radial position at which this occurs is defined as the inner boundary of the track. The outer boundary is found in similar fashion. The track center is computed as the midpoint between such inner and outer boundaries.