Abstract: Logic blocks in a synthesized logic design that have specified inputs are identified by performing a two-pass analysis of the synthesized logic design. A number of levels is specified. A forward linear trace is performed to identify inputs at each level for each logic block, without regard to the specific function of each logic block. A list of potential equivalency points is generated from the forward linear trace. A reverse logical trace is then performed from the potential equivalency points to identify equivalent logic. When no equivalent logic exists, the analysis can specify one or more additional inputs, or one or more missing inputs, to determine whether similar logic exists that could be replicated and modified to achieve the desired function.

Abstract: Logic blocks in a synthesized logic design that have specified inputs are identified by performing a two-pass analysis of the synthesized logic design. A number of levels is specified. A forward linear trace is performed to identify inputs at each level for each logic block, without regard to the specific function of each logic block. A list of potential equivalency points is generated from the forward linear trace. A reverse logical trace is then performed from the potential equivalency points to identify equivalent logic. When no equivalent logic exists, the analysis can specify one or more additional inputs, or one or more missing inputs, to determine whether similar logic exists that could be replicated and modified to achieve the desired function.

Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.