Patents by Inventor Lance Russell
Lance Russell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8689046Abstract: Accurate recovery of a primary server at a recovery server is accomplished with reduced network overhead by maintaining at the recovery server checkpoints taken over time of the primary server and an intention log of logical transactions pending and complete by the primary server. The recovery server is brought to the operational state of the primary server as of failure at the primary server by recovering the most recent checkpoint and then executing the transactions indicated by the intention log as received but not complete as of the time that the checkpoint was taken.Type: GrantFiled: November 5, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: David J. Craft, Lance Russell
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Publication number: 20120117421Abstract: Accurate recovery of a primary server at a recovery server is accomplished with reduced network overhead by maintaining at the recovery server checkpoints taken over time of the primary server and an intention log of logical transactions pending and complete by the primary server. The recovery server is brought to the operational state of the primary server as of failure at the primary server by recovering the most recent checkpoint and then executing the transactions indicated by the intention log as received but not complete as of the time that the checkpoint was taken.Type: ApplicationFiled: November 5, 2010Publication date: May 10, 2012Applicant: International Business Machines CorporationInventors: David J. Craft, Lance Russell
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Publication number: 20080098184Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Inventors: Matthew Huras, Thomas Mathews, Lance Russell
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Publication number: 20070240162Abstract: Automated or autonomic techniques for managing deployment of one or more resources in a computing environment based on varying workload levels. The automated techniques may comprise predicting a future workload level based on data associated with the computing environment. Then, an estimation is performed to determine whether a current resource deployment is insufficient, sufficient, or overly sufficient to satisfy the future workload level. Then, one or more actions are caused to be taken when the current resource deployment is estimated to be insufficient or overly sufficient to satisfy the future workload level. Actions may comprise resource provisioning, resource tuning and/or admission control.Type: ApplicationFiled: June 15, 2007Publication date: October 11, 2007Applicant: International Business Machines CorporationInventors: David Coleman, Steven Froehlich, Joseph Hellerstein, Lawrence Hsiung, Edwin Lassettre, Todd Mummert, Mukund Raghavachari, Lance Russell, Maheswaran Surendra, Noshir Wadia, Peng Ye
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Publication number: 20070233897Abstract: In a computer system divided into multiple separate workload partitions, wherein at least one of the partitions contains multiple applications, and a loopback interface is made available to each partition, a method is provided for routing packets from one application to another application. In one embodiment of the invention, each packet to be routed from one application to another application in the same home partition comprises a first packet, and all other packets comprise second packets. The method comprises the steps of assigning the same pre-specified IP address to each of the first packets, and routing each of the first packets from its home partition to a loopback interface at the IP network processing layer. The method further includes marking the first packets to identify the home partition of each first packet, and directing the marked first packets to a mechanism configured to deliver each first packet only to its home partition, in response to the markings.Type: ApplicationFiled: April 4, 2006Publication date: October 4, 2007Inventors: David Craft, Vinit Jain, Lance Russell, Edward Shvartsman
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Publication number: 20070038678Abstract: A method and system for enabling dynamic matching of storage utilization characteristics of a host system application with the characteristics of the available storage pools of an attached distributed storage system, in order to provide an optimal match between the application and selected storage pool. An abstraction manager is provided, enhanced with a storage device configuration utility/module, which performs a series of tasks to (1) obtain/collect the correct configuration information from each connected storage device or storage pools and/or (2) calculate the configuration information when the information is not readily available. The storage device configuration module then normalizes, collates and matches the configuration information to the various applications running on the host system and/or outputs the information to a user/administrator of the host system via a software interface.Type: ApplicationFiled: August 5, 2005Publication date: February 15, 2007Inventors: James Allen, Matthew Huras, Thomas Mathews, Lance Russell
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Publication number: 20070027999Abstract: A system for coordinating error tracking, level setting and reporting among the various layers/components of a distributed storage system. Each component of the distributed system includes a trigger generation and response (TGR) utility, which generates an error tracking trigger (ETT), comprising: (1) an action that the initiator wants the stack's error tracking mechanisms to take; (2) a message that the initiator wants the stack to immediately post in its logs; and (3) a route/direction that the trigger is to be transmitted through the stack. The ETT is transmitted one layer at a time through the stack, and each intervening layer of the stack is equipped with a utility to examine the ETT and take the appropriate action(s), designated by the trigger. An error log is maintained by each layer of the stack and used to record information about the error and enable user determination of the source, timing and cause of errors.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Inventors: James Allen, Matthew Kalos, Thomas Mathews, Lance Russell
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Publication number: 20060248290Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.Type: ApplicationFiled: April 28, 2005Publication date: November 2, 2006Applicant: International Business Machines CorporationInventors: Matthew Huras, Thomas Mathews, Lance Russell
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Publication number: 20060235990Abstract: A method, apparatus, and computer instructions for controlling data flow. A control message is formed for the data flow in response to an event while the data flow is occurring. The control message includes a data type, an action, and a duration. The control message is sent to a receiver data processing system, wherein the receiver data processing system modifies the data flow to the data processing system using the control message.Type: ApplicationFiled: April 19, 2005Publication date: October 19, 2006Applicant: International Business Machines CorporationInventors: James Allen, Matthew Kalos, Thomas Mathews, George Penokie, Lance Russell, Gail Spear
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Patent number: 7120752Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.Type: GrantFiled: September 5, 2003Date of Patent: October 10, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Mark Wilson, Fong Pong, Lance Russell, Tung Nguyen, Lu Xu
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Publication number: 20050198401Abstract: A method and structure for communicating in a communications network comprising at least one communication virtualizer; a plurality of network-attached store computers connected to the communication virtualizer, wherein the plurality of network-attached store computers are configured to appear as a single available network-attached store computer; and at least one client computer connected to the communication virtualizer.Type: ApplicationFiled: January 29, 2004Publication date: September 8, 2005Inventors: Edward Chron, Paul Morgan, Lance Russell
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Patent number: 6880045Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.Type: GrantFiled: October 12, 2001Date of Patent: April 12, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Fong Pong, Lance Russell, Tung Nguyen
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Patent number: 6874065Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a “flush” command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a “flush request” is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.Type: GrantFiled: February 26, 1999Date of Patent: March 29, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Fong Pong, Lance Russell, Tung Nguyen
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Publication number: 20050033925Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.Type: ApplicationFiled: September 5, 2003Publication date: February 10, 2005Inventors: Kenneth Wilson, Fong Pong, Lance Russell, Tung Nguyen, Lu Xu
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Patent number: 6745294Abstract: A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.Type: GrantFiled: June 8, 2001Date of Patent: June 1, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kenneth Mark Wilson, Fong Pong, Lance Russell, Tung Nguyen, Lu Xu
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Patent number: 6675262Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.Type: GrantFiled: June 8, 2001Date of Patent: January 6, 2004Assignee: Hewlett-Packard Company, L.P.Inventors: Kenneth Mark Wilson, Fong Pong, Lance Russell, Tung Nguyen, Lu Xu
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Publication number: 20020188730Abstract: A method and system for handing-off TCP states in a communication network. Specifically, the present invention allows for handing-off TCP states between nodes in an associated network that is optimized for frequent handoff of TCP states. The handoff occurs between dynamically loadable modules that wrap around the TCP/IP stack located at a front-end server and a selected back-end server. A handoff protocol implemented by the loadable modules works within the kernel level of the existing TCP/IP code. As such, no changes to the existing TCP/IP code is necessary. The loadable modules at the front-end are able to select a back-end server depending on the content of the HTTP request, coordinate handing off TCP states, and forward packets to the back-end server. Loadable modules at the selected back-end modify response packets to reflect the proper TCP state of the front-end server.Type: ApplicationFiled: June 12, 2001Publication date: December 12, 2002Inventors: Wenting Tang, Ludmila Cherkasova, Lance Russell
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Publication number: 20020073071Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.Type: ApplicationFiled: October 12, 2001Publication date: June 13, 2002Inventors: Fong Pong, Lance Russell, Tung Nguyen
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Patent number: 6360231Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.Type: GrantFiled: February 26, 1999Date of Patent: March 19, 2002Assignee: Hewlett-Packard CompanyInventors: Fong Pong, Lance Russell, Tung Nguyen