Abstract: Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.

Abstract: Devices and techniques for authenticated modification of a storage device are described herein. A data transmission, received at an interface of the storage device, can be decoded to obtain a command, a set of input identifications, and a first signature corresponding to data identified by the input identifications. Members of the set of input identifications can be marshalled to produce an input set. A cryptographic engine of the storage device can be invoked on the input set to produce a second signature from the input set. The first signature is and the second signature are compared to determine a match. In response to the match, the input set can be written to a secure portion of the storage device.

Abstract: Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.

Abstract: Various examples are directed to secure memory arrangements and methods of using the same. A gateway device of the secure computing system may receiving a first message from an external system. The first message may comprise a first message payload data and first asymmetric access data. The gateway device may determine that the first asymmetric access data matches the first message payload data based at least in part on an external system public key. The gateway device may access a first system controller symmetric key associated with a first system controller in communication with the gateway device and generate a first symmetric access data based at least in part on the first system controller symmetric key and the first message payload data. The gateway device may send the first message payload data and the first symmetric access data to the first system controller.

Abstract: System and techniques for storage device hash production are described herein. A data transmission received at an interface of the storage device is decoded. Here, the data transmission includes a command corresponding to a hash operation, a set of input identifications, and an output identification. Members of the set of input identifications are marshalled to produce an input set. A hash engine of the storage device is invoked on the input set to produce a hash product. The hash product is stored in a portion of the storage device corresponding to the output identification.

Abstract: Various examples are directed to secure memory arrangements and methods of using the same. A gateway device of the secure computing system may receiving a first message from an external system. The first message may comprise a first message payload data and first asymmetric access data. The gateway device may determine that the first asymmetric access data matches the first message payload data based at least in part on an external system public key. The gateway device may access a first system controller symmetric key associated with a first system controller in communication with the gateway device and generate a first symmetric access data based at least in part on the first system controller symmetric key and the first message payload data. The gateway device may send the first message payload data and the first symmetric access data to the first system controller.

Abstract: Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.

Abstract: Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord.

Abstract: A secure memory device for secure data storage and related method are provided. The device may include an accessible data storage area configured to store data, a start location register that points to a start of the accessible data storage area, and a size-related register that allows a size of the accessible data storage area to be determined. A secret area comprises a device secret that is a value unique to the device, and that is not accessible from external to the device, and is accessible under at least one predefined conditions internal to the device, an access control element configured to prevent external access to the secret data. A generator generates a derived secret based on the storage data and the secret data that is usable to authenticate the storage data. The device may also include a memory bus over which the derived secret is communicated.

Abstract: Various examples are directed to secure memory arrangements and methods of using the same. A gateway device of the secure computing system may receiving a first message from an external system. The first message may comprise a first message payload data and first asymmetric access data. The gateway device may determine that the first asymmetric access data matches the first message payload data based at least in part on an external system public key. The gateway device may access a first system controller symmetric key associated with a first system controller in communication with the gateway device and generate a first symmetric access data based at least in part on the first system controller symmetric key and the first message payload data. The gateway device may send the first message payload data and the first symmetric access data to the first system controller.

Abstract: Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.

Abstract: System and techniques for storage device hash production are described herein. A data transmission received at an interface of the storage device is decoded. Here, the data transmission includes a command corresponding to a hash operation, a set of input identifications, and an output identification. Members of the set of input identifications are marshalled to produce an input set. A hash engine of the storage device is invoked on the input set to produce a hash product. The hash product is stored in a portion of the storage device corresponding to the output identification.

Abstract: Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU) and a nonvolatile memory device operably coupled to the CPU. The nonvolatile memory device can include a memory that stores pre-measurement instructions that are executable by the nonvolatile memory upon startup, but not executable by the CPU upon startup. In operation, the pre-measurement instructions direct the nonvolatile memory to take a measurement of at least a portion of its contents and to cryptographically sign the measurement to indicate that the measurement was taken by the nonvolatile memory device. In one embodiment, the CPU can use the measurement to determine whether the nonvolatile memory device is trustworthy.

Abstract: Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU) and a nonvolatile memory device operably coupled to the CPU. The nonvolatile memory device can include a memory that stores pre-measurement instructions that are executable by the nonvolatile memory upon startup, but not executable by the CPU upon startup. In operation, the pre-measurement instructions direct the nonvolatile memory to take a measurement of at least a portion of its contents and to cryptographically sign the measurement to indicate that the measurement was taken by the nonvolatile memory device. In one embodiment, the CPU can use the measurement to determine whether the nonvolatile memory device is trustworthy.

Abstract: An apparatus and method for providing a source of random numbers are generally described. In one example, an apparatus includes one or more storage elements having a selected voltage and a trip point, the voltage being close enough to the trip point such that random telegraph signal (RTS) noise associated with the elements is a determinant of whether the read voltage is above or below the trip point.

Abstract: A wireless device incorporates a nonvolatile memory that dynamically controls a swapping or mapping of bit pairs for a selected memory region to optimize programming times.

Abstract: A memory device includes a memory array with a programming region to store data. The programming region includes a plurality of memory cells and has an associated flag bit. Logic is coupled to the memory array. The logic is to compare data stored in the programming region to a desired programmed value, and to determine a number of changing bits. The logic may further set or clear the associated flag bit, depending on the number of changing bits.

Abstract: A method and apparatus is described herein for compressing a binary image in memory and decompressing a portion memory in response to a request, without using a compression index table to find relocated compressed code. A binary image is traversed in windows. Each selected window is compressed to form compressed windows having a compressed portion and an available memory portion. Static data is backfilled in available memory portions to achieve efficient compression. Upon receiving a request to a specific physical address, the compressed portion of that physical location is decompressed and provided for execution without using a compression index table, as the compressed code portion was not relocated from its original physical location.

Abstract: An apparatus and method for providing a source of random numbers are generally described. In one example, an apparatus includes one or more storage elements having a selected voltage and a trip point, the voltage being close enough to the trip point such that random telegraph signal (RTS) noise associated with the elements is a determinant of whether the read voltage is above or below the trip point.