Patents by Inventor Lance W. Shelton
Lance W. Shelton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9513830Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.Type: GrantFiled: October 12, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Kenneth Scianna, Lance W. Shelton
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Patent number: 9501235Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: February 1, 2016Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Publication number: 20160283327Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: Holloway H. FROST, Don D. DAVIS, Adrian P. GLOVER, Lance W. SHELTON
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Publication number: 20160162211Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: ApplicationFiled: February 1, 2016Publication date: June 9, 2016Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 9361984Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.Type: GrantFiled: July 2, 2013Date of Patent: June 7, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Don D. Davis, Adrian P. Glover, Lance W. Shelton
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Publication number: 20160034218Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.Type: ApplicationFiled: October 12, 2015Publication date: February 4, 2016Inventors: Holloway H. FROST, Charles J. CAMP, Kenneth SCIANNA, Lance W. SHELTON
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Patent number: 9250991Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: December 31, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 9158708Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.Type: GrantFiled: December 30, 2014Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Kenneth Scianna, Lance W. Shelton
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Publication number: 20150113341Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: ApplicationFiled: December 31, 2014Publication date: April 23, 2015Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Publication number: 20150113211Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.Type: ApplicationFiled: December 30, 2014Publication date: April 23, 2015Inventors: Holloway H. FROST, Charles J. Camp, Ken Scianna, Lance W. Shelton
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Patent number: 8943263Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: May 28, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 8930622Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a FLASH memory system. The methods and apparatuses involve a system controller for a plurality of FLASH memory devices in the FLASH memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.Type: GrantFiled: December 6, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Ken Scianna, Lance W. Shelton
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Patent number: 8775772Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.Type: GrantFiled: December 21, 2009Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: James A. Fuxa, Lance W. Shelton, Justin C. Haggard
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Publication number: 20130294163Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.Type: ApplicationFiled: July 2, 2013Publication date: November 7, 2013Inventors: Holloway H. FROST, Don D. DAVIS, Adrian P. GLOVER, Lance W. SHELTON
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Patent number: 8495423Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.Type: GrantFiled: December 30, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Don D. Davis, Adrian P. Glover, Lance W. Shelton
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Publication number: 20130124788Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a FLASH memory system. The methods and apparatuses involve a system controller for a plurality of FLASH memory devices in the FLASH memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.Type: ApplicationFiled: December 6, 2012Publication date: May 16, 2013Applicant: TEXAS MEMORY SYSTEMS, INC.Inventors: Holloway H. FROST, Charles J. CAMP, Ken SCIANNA, Lance W. SHELTON
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Publication number: 20120233391Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: ApplicationFiled: May 28, 2012Publication date: September 13, 2012Applicant: TEXAS MEMORY SYSTEMS, INC.Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 8190842Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: September 10, 2010Date of Patent: May 29, 2012Assignee: Texas Memory Systems, Inc.Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Publication number: 20110219259Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.Type: ApplicationFiled: December 30, 2010Publication date: September 8, 2011Applicant: TEXAS MEMORY SYSTEMS, INC.Inventors: Holloway H. Frost, Don D. Davis, Adrian P. Glover, Lance W. Shelton
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Publication number: 20110040927Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.Type: ApplicationFiled: December 21, 2009Publication date: February 17, 2011Applicant: TEXAS MEMORY SYSTEMS, INC.Inventors: James A. Fuxa, Lance W. Shelton, Justin C. Haggard