Patents by Inventor Landy Wang

Landy Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120233438
    Abstract: A system and method for maintaining a pagefile of a computer system using a technique of reserving portions of the pagefile for related memory pages. Pages near one another in a virtual memory space often store related information and it is therefore beneficial to ensure that they are stored near each other in the pagefile. This increases the speed of reading data out of the pagefile because total seek time of a disk drive that stores the pagefile may decrease when adjacent pages in a virtual memory address space are read back from the disk drive. By implementing a reservation system that allows related pages to be stored adjacent to one another, the efficiency of memory management to of the computer system is increased.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 13, 2012
    Applicant: Microsoft Corporation
    Inventors: Yevgeniy M. Bak, Mehmet Iyigun, Landy Wang
  • Patent number: 8250331
    Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 21, 2012
    Assignee: Microsoft Corporation
    Inventors: Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin
  • Publication number: 20120137167
    Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: Microsoft Corporation
    Inventors: Garrett Leischner, Andrew J. Lagattuta, Matthew Jeremiah Eason, Landy Wang, John R. Douceur, Baskar Sridharan, Edmund B. Nightingale
  • Patent number: 8028148
    Abstract: Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable image. Moreover, performance improvements are implemented over traditional systems that enable relative addressed instruction to be resolved at runtime. In this regard, a method is provided that identifies a randomized location to load the executable image into a memory address space. Then, data that may be used to resolve the relative addressed instruction is loaded and maintained in memory. At runtime when pages that store relative addressed instructions are accessed, an arithmetic operation is performed to resolve the relative addressed instruction. As a result, only those relative addressed instructions on pages accessed during program execution are resolved.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 27, 2011
    Assignee: Microsoft Corporation
    Inventors: Richard Shupak, Landy Wang
  • Publication number: 20110145552
    Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Inventors: Koichi Yamada, Gad Sheaffer, Jan Gray, Landy Wang, Martin Taillefer, Arun Kishan, Ali-Reza Adl-Tabatabai, David Callahan
  • Publication number: 20110113432
    Abstract: Compressed storage management includes assigning a selection priority and a priority level to multiple data units stored in an uncompressed portion of a storage resource. The management can further include compressing data units and storing the compressed data units in a compressed portion of the storage resource. The data units in the compressed portion are stored in regions, which each store data units having the same selection priority or the same selection priority level.
    Type: Application
    Filed: January 13, 2011
    Publication date: May 12, 2011
    Applicant: Microsoft Corporation
    Inventors: Cenk Ergan, Mehmet Iyigun, Yevgeniy Bak, Benjamin A. Mickle, Alexander Kirshenbaum, Landy Wang
  • Patent number: 7895242
    Abstract: In accordance with one or more aspects, compressed storage management in a system includes determining which of multiple data units stored in an uncompressed portion of the storage resource are to be compressed and stored in a compressed portion of the storage resource. The management can further include returning one or more regions of the compressed portion for use in the uncompressed portion in response to storage resource pressure in the system, as well as compacting regions in the compressed portion to fill empty gaps in the compressed portion.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 22, 2011
    Assignee: Microsoft Corporation
    Inventors: Cenk Ergan, Mehmet Iyigun, Yevgeniy Bak, Benjamin A Mickle, Alexander Kirshenbaum, Landy Wang
  • Publication number: 20100332721
    Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Koichi Yamada, Gad Sheaffer, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun Kishan, David Callahan, Jan Gray, Vadim Bassin
  • Patent number: 7861121
    Abstract: A method and system for verifying computer system drivers such as kernel mode drivers. A driver verifier sets up tests for specified drivers and monitors the driver's behavior for selected violations that cause system crashes. In one test, the driver verifier allocates a driver's memory pool allocations from a special pool bounded by inaccessible memory space to test for the driver's accessing memory outside of the allocation. The driver verifier also marks the space as inaccessible when it is deallocated, detecting a driver that accesses deallocated space. The driver verifier may also provide extreme memory pressure on a specific driver, or randomly fail requests for pool memory. The driver verifier also checks call parameters for violations, performs checks to ensure a driver cleans up timers when deallocating memory and cleans up memory and other resources when unloaded. An I/O verifier is also described for verifying drivers use of I/O request packets.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: December 28, 2010
    Assignee: Microsoft Corporation
    Inventor: Landy Wang
  • Patent number: 7788464
    Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 31, 2010
    Assignee: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 7587566
    Abstract: The present invention is directed to a method and system for minimizing memory access latency during realtime processing. The method includes a mechanism for marking information that will be accessed during realtime processing. The marked information may include code, data, heaps, stacks, as well as other information. The method includes support for locking down all of the marked information so that it is present in a computing machine's physical memory so that no page faults will be incurred during realtime processing. The method additionally enables realtime processing code to allocate and free memory in a non-blocking manner. It does so by enabling the creation of heaps for use during realtime processing, wherein each heap supports allocating and freeing memory in a non-blocking fashion. Each heap tracks freed memory blocks using individual non-blocking tracking lists for each memory block size supported by that heap.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 8, 2009
    Assignee: Microsoft Corporation
    Inventors: Joseph C. Ballantyne, Landy Wang
  • Publication number: 20090112949
    Abstract: In accordance with one or more aspects, compressed storage management in a system includes determining which of multiple data units stored in an uncompressed portion of the storage resource are to be compressed and stored in a compressed portion of the storage resource. The management can further include returning one or more regions of the compressed portion for use in the uncompressed portion in response to storage resource pressure in the system, as well as compacting regions in the compressed portion to fill empty gaps in the compressed portion.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: Cenk Ergan, Mehmet Iyigun, Yevgeniy Bak, Benjamin A Mickle, Alexander Kirshenbaum, Landy Wang
  • Patent number: 7496730
    Abstract: Access bit contained in a page table entry is utilized for reducing the number of translation buffer flushes that an operating system needs to issue. A translation buffer flush occurs only when a page table entry is to become invalid and the Access bit of the page table entry is set.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: February 24, 2009
    Assignee: Microsoft Corporation
    Inventors: Landy Wang, Arun Kishan
  • Patent number: 7398430
    Abstract: A system and method for self-diagnosing a likely cause of a system crash is disclosed. A mechanism within an operating system checks for the existence of a stop code at startup of the machine. The existence of the stop code indicates that the system crashed during the previous session, and the type of system crash. The mechanism may read the stop code and implement a self-diagnostic procedure that corresponds to that stop code. In this manner, the mechanism may automate many of the tasks normally performed by humans, such as a system administrator, to self-diagnose the likely cause of the crash. If the crash occurs again, the mechanism, through the tracking procedures automatically implemented, may identify and report to a system administrator the likely cause of the crash, e.g. the particular faulty driver or configuration error.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: July 8, 2008
    Assignee: Microsoft Corporation
    Inventors: Landy Wang, Matthew D. Hendel
  • Patent number: 7395496
    Abstract: The present invention utilizes pageable pool memory to provide, via a data verifier component, data verification information for storage mediums. By allowing the utilization of pageable pool memory, overflow from the pageable pool memory is paged and stored in a virtual memory space on a storage medium. Recently accessed verification information is stored in non-pageable memory, permitting low latency access. One instance of the present invention synchronously verifies data when verification information is accessible in physical system memory while deferring processing of data verification when verification information is stored in paged memory. Another instance of the present invention allows access to paged verification information in order to permit synchronous verification of data.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: July 1, 2008
    Assignee: Microsoft Corporation
    Inventors: Ervin Peretz, Karan Mehra, Landy Wang
  • Publication number: 20080155168
    Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080134174
    Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080133875
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Microsoft Corporation
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080126742
    Abstract: Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable image. Moreover, performance improvements are implemented over traditional systems that enable relative addressed instruction to be resolved at runtime. In this regard, a method is provided that identifies a randomized location to load the executable image into a memory address space. Then, data that may be used to resolve the relative addressed instruction is loaded and maintained in memory. At runtime when pages that store relative addressed instructions are accessed, an arithmetic operation is performed to resolve the relative addressed instruction. As a result, only those relative addressed instructions on pages accessed during program execution are resolved.
    Type: Application
    Filed: September 6, 2006
    Publication date: May 29, 2008
    Applicant: Microsoft Corporation
    Inventors: Richard Shupak, Landy Wang
  • Publication number: 20070168739
    Abstract: A system and method for self-diagnosing a likely cause of a system crash is disclosed. A mechanism within an operating system checks for the existence of a stop code at startup of the machine. The existence of the stop code indicates that the system crashed during the previous session, and the type of system crash. The mechanism may read the stop code and implement a self-diagnostic procedure that corresponds to that stop code. In this manner, the mechanism may automate many of the tasks normally performed by humans, such as a system administrator, to self-diagnose the likely cause of the crash. If the crash occurs again, the mechanism, through the tracking procedures automatically implemented, may identify and report to a system administrator the likely cause of the crash, e.g. the particular faulty driver or configuration error.
    Type: Application
    Filed: October 12, 2006
    Publication date: July 19, 2007
    Applicant: Microsoft Corporation
    Inventors: Landy Wang, Matthew Hendel