Patents by Inventor Lane Byron Quibodeaux

Lane Byron Quibodeaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for detecting errors in a backplane frame
    Patent number: 6934305
    Abstract: A method of generating a parity value is disclosed. The method includes reading a word from a data stream, determining if the word should be included in a parity calculation, and including the word in the parity calculation, if the word should be included in the parity calculation, and ignoring the word otherwise.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: August 23, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Douglas E. Duschatko, Lane Byron Quibodeaux, Robert A. Hall, Andrew J. Thurston
  • Concatenation detection across multiple chips
    Patent number: 6735197
    Abstract: An apparatus and method for detecting concatenation of payload data for an communication circuit is disclosed, wherein the payload data is dispersed over a first integrated circuit and one or more subsequent integrated circuits. The method and apparatus include determining whether each of the one or more subsequent integrated circuits have all channels therein designated as concatenation slaves, and communicating the determination to the first integrated circuit, the determination indicating that the one or more subsequent integrated circuits. According to an embodiment, the method and apparatus further include coupling the first integrated circuits to the one or more subsequent integrated circuits.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: May 11, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Douglas E. Duschatko, Lane Byron Quibodeaux, Robert A. Hall, Andrew J. Thurston