Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: A method of managing the charge stored by a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, involves supplying each capacitor stage with charge current via a common charging terminal; separately measuring a stored potential of each capacitor stage in the series arrangement; selectively removing a controlled amount of charge from each of the capacitor stages individually) while the series arrangement is receiving the charge current from the common charging terminal; and maintaining each capacitor stage at a substantially equal stored potential.

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power, the backup power provided by at least one capacitor; logic to create, while the capacitor is available as the backup power supply to the external system, a transient elevation of the capacitor's stored potential above a upper predetermined operating potential of the capacitor; logic to obtain measurements of the capacitor's output voltage during the transient elevation of the capacitor's stored potential; and logic to determine a capacitance of the capacitor from the measurements; the device comprising multiple capacitors in series; logic to discharge each capacitor in series individually from the others; and logic to monitor for overcharging of any of the capacitors in series, and, during charging of the capacitors in series, to operate the discharge logic for any capacitor in the series that is in danger of overcharging.

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements.

Abstract: “A circuit includes a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage receives charge current via a common charging terminal. A controller is configured to separately measure a stored potential of each capacitor stage in the series arrangement. The circuit includes logic to selectively remove a controlled amount of charge from each capacitor stage individually (discharge logic), and logic to operate the discharge logic to maintain each capacitor stage in the series arrangement at a substantially equal stored potential (balancing logic).

Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.

Abstract: Methods and apparatus for adding an autonomous controller to an existing architecture such as by way of example, portable devices such as cell phones, MP3 players, and digital cameras. A circuit interposed between the memory card and the system controller of the device is controllable to couple the memory card to the system controller, or to couple the memory card to a high speed I/O controller on the circuit. When the memory card is coupled to the high speed I/O controller on the circuit, the circuit provides signals to the system controller indicative of a memory card removal event. In systems having an I/O connection such as a USB connection, the circuit also disconnects that connection from the system controller, provides signals to the system control indicative of a USB disconnect and connects the I/O connection to the memory card through a high speed data transfer unit to provide a higher speed I/O capability. Various features and capabilities are disclosed.

Abstract: An impulsive communication activated device for connection to a computer input port for controlling a computer, is disclosed. The disclosed device includes an output connector for communicating with the computer input port, and includes a sensor for detecting an impulsive communication such as a hand clap or other predetermined input, to generate an impulsive signal. The disclosed device includes a comparator for responding to both a reference signal and to the impulsive signal, and to determine if the impulsive signal differs substantially from the reference signal to generate a start signal. The disclosed device includes a logic circuit responsive to the start signal for generating a predetermined computer command signal to control the computer.

Abstract: A method and apparatus for automatically detecting the memory size of a serial peripheral interface (SPI) device. Specifically, the present invention describes an SPI interface circuit including a memory controller chip, an EEPROM, a sensing circuit, and a pulldown resistor. In one embodiment, a “READ” command from the controller to the SPI device is sent in a first byte of information transferred between the controller and SPI device. The data Input/Output (D-IO) pin is then driven low for the second byte of information. Next, the D-IO pin is floated and the pin assumes a logic “0” level due to a pulldown resistor. Subsequently, a sensing circuit can detect when and if a non-zero data value passes from the SPI device to the memory controller chip to determine the memory size of the SPI device or the absence of an SPI device.

Abstract: A method for describing a user programmable logic function generator in a Hardware Description Language (HDL), e.g., Verilog is disclosed. The logic function generator includes a multiplexer having a plurality of select inputs and a plurality of programmable data inputs. The logic function generator which can be implemented exclusively with gates generates a function of the select inputs. The logic function generator receives user's input through the plurality of data inputs to generate an output of a desired logic function of the select inputs. The logic function generator is entirely made of standard gates, which is amenable to representation by and inclusion in standard design libraries. The invention further provides a user with greater flexibility by allowing a cascading of a number of logic function generators for generating multi-variable functions generated of a greater number of select inputs.

Abstract: A circuit for a use in a control system of a peripheral device that is dedicated to tasks related to communication with a host computer via a universal serial bus (USB). The invention affords a USB dedicated circuit that is configured to allow a host computer to recognize and enumerate a device as a USB configured device without the use of the device's micro-controller. In another aspect of the invention a USB dedicated circuit that is configured to perform other USB related tasks in conjunction with the device's micro-controller in a more efficient manner than a device operating solely with a micro-controller.

Abstract: A computer input system for a computer generating images appearing on a screen. For the purpose of modifying the images appearing on the screen, a light generating device causes an auxiliary light image to appear on the screen. An image sensor responds to the auxiliary image, and a circuit responds to the sensor for causing auxiliary image information to be stored concerning the auxiliary light image. Another circuit responds to the stored auxiliary image information to supply the auxiliary light image information to the computer for utilization therein.