Patents by Inventor Lanfa Wang

Lanfa Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11849016
    Abstract: Techniques are disclosed for performing time synchronization at a plurality of computing devices in a network. In one example, a method comprising obtaining timestamp data in accordance with a synchronization operation for a timing protocol; computing a skewness estimate and an offset estimate from the timestamp data by executing a regression analysis, wherein the regression analysis is configured to train a first model to predict the offset estimate and the skewness estimate, the offset estimate comprising a clock time difference between the first clock and the second clock; computing a corrected skewness estimate and a corrected offset estimate based on a second model having parameters based on the offset estimate and the skewness estimate; and modifying a current time value of at least one of the first clock or the second clock based on at least one of the corrected offset estimate or the corrected skewness estimate.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: December 19, 2023
    Assignee: Equinix, Inc.
    Inventors: Lanfa Wang, Danjue Li, Mustafa Arisoylu
  • Patent number: 11520372
    Abstract: Techniques are disclosed for performing time synchronization for a plurality of computing devices without relying upon a minimum measured delay. In one example, processing circuitry obtains time stamp data in accordance with an iteration of a synchronization operation for a timing protocol, wherein the time stamp data describes one or more measured delays for a path between a first computing device and a second computing device, computes a skewness estimate from the time stamp data using a regression analysis, the skewness estimate comprising a frequency difference between a first clock at the first computing device and a second clock at the second computing device, computes an offset estimate between the first clock and the second clock by applying a prediction model to the skewness estimate; and corrects at least one of the first clock or the second clock based at least on the offset estimate.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 6, 2022
    Assignee: EQUINIX, INC.
    Inventors: Lanfa Wang, Danjue Li
  • Publication number: 20220206865
    Abstract: In general, this disclosure describes techniques for configuring and provisioning, with a distributed artificial intelligence (AI) fabric controller, network resources in an AI fabric for use by AI applications. In one example, the AI fabric controller is configured to discover available resources communicatively coupled to a cloud exchange; obtain a set of candidate solutions, each candidate solution of the set of candidate solutions comprising an AI application and a configuration of resources for use by the AI application; filter, based on one or more execution metrics corresponding to each of the candidate solutions, the set of candidate solutions to generate a filtered set of candidate solutions; generate provisioning scripts for the filtered set of candidate solutions; execute the provisioning scripts to provision resources for each candidate solution in the filtered set of candidate solutions; and create an execution environment for each candidate solution in the filtered set of candidate solutions.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 30, 2022
    Inventors: Kaladhar Voruganti, Danjue Li, Lanfa Wang, Mustafa Arisoyfu, Ravi Kiran Pasula, Rodney Martin Elder, Zoe Liu
  • Patent number: 11206095
    Abstract: Techniques are disclosed for performing time synchronization for a plurality of computing devices that exhibit asymmetric path delay. In one example, processing circuitry receives data indicative of a graph comprising a plurality of nodes and vertices, wherein each node represents a clock and each vertex represents a bidirectional path between two clocks. Each bidirectional path has a first path delay in a first direction that is different from a second path delay in a second direction. The processing circuitry determines one or more closed loops in the graph and a path delay of the closed loop. The processing circuitry applies a minimization function to the path delay of each closed loop to determine values for the first and second path delays of each bidirectional path. The processing circuitry applies, based on the values for the first and second path delays of each bidirectional path, a time correction to a clock.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 21, 2021
    Assignee: Equinix, Inc.
    Inventors: Lanfa Wang, Danjue Li
  • Patent number: 11063738
    Abstract: Techniques are disclosed for performing time synchronization at a plurality of computing devices in a network. In one example, a method comprising obtaining time stamp data in accordance with a synchronization operation for a timing protocol; computing a skewness estimate and an offset estimate from the time stamp data by executing, over a number of iterations, a weighted regression analysis targeting at least one bound of the time stamp data, the skewness estimate comprising a frequency difference between a first clock at a first computing device and a second clock at a second computing device, the offset estimate comprising a clock time difference between the first clock and the second clock; and applying a clock time correction to the at least one of the first clock or the second clock based the offset estimate.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 13, 2021
    Assignee: EQUINIX, INC.
    Inventor: Lanfa Wang