Abstract: A display device includes a first display unit emitting a green light having a first output spectrum corresponding to a highest gray level of the display device and a second display unit emitting a blue light having a second output spectrum corresponding to the highest gray level of the display device. The first output spectrum has a main wave with a first peak. The second output spectrum has a main wave with a second peak and a sub wave with a sub peak. The second peak corresponds to a main wavelength, the sub peak corresponds to a sub wavelength, and the main wavelength is less than the sub wavelength. An intensity of the second peak is greater than an intensity of the sub peak and an intensity of the first peak.

Abstract: A method in one embodiment creates a model of an authentic IC for use in comparisons with counterfeit ICs. The model can be created by determining a first or initial set of points of interest (POIs) on the simulated physical (e.g., gate level) layout and simulating side channel leakage from each POI and then expanding the size of the POI and repeating the simulation and comparing successive simulation results (between successive sizes of POIs for a given POI) to determine if a solution for the size of the POI has converged. The final POIs are then processed in a simulation that can use multiple payloads (e.g., cryptographic data) over the entire set of final POIs, and the resulting data set can be used to create the model.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: Provided are a wafer defect tracing method and apparatus, an electronic device and a computer readable medium. The method includes: obtaining defect data of a wafer; obtaining position data of fail bits of the wafer; determining a defect area of a storage block in the wafer according to the defect data; determining a fail bit count of the storage block in the wafer according to the position data of the fail bits; processing the defect area and the fail bit count of each storage block in the wafer, so as to obtain a correlation coefficient; and determining an abnormal reason for the fail bits of the wafer according to the correlation coefficient.

Abstract: An electronic device includes a light emitting diode and a light converting layer disposed on the light emitting diode. The electronic device emits a green output light under an operation of a highest brightness. The green output light has an output spectrum. An intensity integral of the output spectrum from 380 nm to 489 nm is defined as a first intensity integral. An intensity integral of the output spectrum from 490 nm to 780 nm is defined as a second intensity integral. A ratio of the first intensity integral over the second intensity integral is defined as a first ratio, and the first ratio is greater than 0% and less than or equal to 7.5%.

Abstract: The present disclosure provides a method of manufacturing a photomask. The method includes: forming a multilayer structure on a substrate; forming a capping layer on the multilayer structure, the capping layer including a ruthenium oxide (RuO) layer; forming a light-absorbing structure on the capping layer; forming a hard mask on the light-absorbing structure; etching the light-absorbing structure to form a recess by using the hard mask as an etch mask, wherein the recess exposes a top portion of the capping layer; and performing a treatment to convert the top portion into a ruthenium nitride (RuN) layer.

Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed. A multilayer structure is formed over the substrate, wherein the multilayer structure includes a plurality of silicon layers and a plurality of molybdenum layers alternately arranged with the plurality of silicon layers. A nitride layer and an oxide layer are formed over the multilayer structure, wherein a total thickness of the nitride layer and a topmost silicon layer is substantially equal to a thickness of each of all other silicon layers of the plurality of silicon layers. A patterned layer is formed over the nitride layer. A semiconductor structure thereof is also provided.

Abstract: A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair regions in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair region by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair region is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.

Abstract: A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.

Abstract: A method for chip collection and a method for chip positioning are provided. The method for chip collection includes that: an image to be detected is obtained; chip position information of a comparison image with a highest matching degree with the image to be detected is obtained from a database; a position of each of detection regions in the image to be detected is obtained based on the chip position information; an image of the detection region is obtained based on the position of each detection region; it is determined whether the image of the detection region includes the chip code image; and when the image of the detection region includes the chip code image, a chip code corresponding to the chip code image identified and the chip code is stored in the database.

Abstract: A local region to be repaired including the fail bit is determined. A preliminary repair LR circuit for repairing the local region to be repaired is determined (S210). A region level of the local region to be repaired is determined (S230) according to the number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and the number of available LR circuits. It is controlled, according to the region level of the local region to be repaired, to repair the fail bit by the GR circuit or the LR circuit (S240).

Abstract: A spin dry etching process includes loading an object into a dry etching system. A dry etching process is performed to the object, and the object is spun while the dry etching process is being performed. The spin dry etching process is performed using a semiconductor fabrication system. The semiconductor fabrication system includes a dry etching chamber in which a dry etching process is performed. A holder apparatus has a horizontally-facing slot that is configured for horizontal insertion of an etchable object therein. The etchable object includes either a photomask or a wafer. A controller is communicatively coupled to the holder apparatus and configured to spin the holder apparatus in a clockwise or counterclockwise direction while the dry etching process is being performed. An insertion of the etchable object into the horizontally-facing slot of the holder apparatus restricts a movement of the object as the dry etching process is performed.

Abstract: A Fail Bit (FB) repair method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing.

Abstract: A method and an apparatus for determining a repair location for a redundancy circuit, and a method for repairing an integrated circuit are provided. At least one fail bit of a chip to be repaired is determined. At least one initial repair location for the redundancy circuit is initially assigned according to the at least one fail bit. At least one potential fail line is determined according to the at least one initial repair location. At least one predicted repair location is determined according to the at least one potential fail line. Each of the at least one predicted repair location is a location with a higher probability that a new fail bit appears. At least one final repair location for the redundancy circuit is determined according to the at least one fail bit and the at least one predicted repair location.

Abstract: A processing method of chip probing data includes: determining a new fail bit generated in an already completed chip probing process; acquiring repair record of the new fail bit, and repair records of bits adjacent to the new fail bit; analyzing the repair records to determine attribute information of the new fail bit and the adjacent bits, the attribute information including at least one of address information, redundant circuit information, element pattern of the new fail bit and chip probing flow; performing classification learning according to the attribute information to acquire a fail bit prediction model; and predicting fail bits to be chip-probed through the fail bit prediction model.

Abstract: A reflection mode photomask includes a multilayer over a substrate. The reflection mode photomask further includes a plurality of absorber stacks over the multilayer. Each absorber stack of the plurality of absorber stacks includes an absorber layer, wherein a material of the absorber layer is selected from the group consisting of tantalum oxynitride and tantalum silicon oxynitride. Each absorber stack of the plurality of absorber stacks further includes an anti-reflective coating (ARC) layer on the absorber layer, wherein a material of the ARC layer is selected from the group consisting of tantalum nitride and tantalum silicon.

Abstract: Disclosed is a method and system for realizing rapid degradation of halogenated organic pollutants in water. The system comprises a hydrodehalogenation reactor, an advanced oxidation reactor, a hydrogen gas supply unit and a control unit. The method comprises: 1) introducing a palladium salt into the hydrodehalogenation reactor and the advanced oxidation reactor, and reducing and loading palladium onto the surfaces of membrane modules; 2) introducing a wastewater containing the halogenated organic pollutants into the hydrodehalogenation reactor, and subjecting the halogenated pollutants to hydrodehalogenation with palladium catalysis; 3) introducing the dehalogenated wastewater into the advanced oxidation reactor, and adding a persulfate into the second reactor body.

Abstract: A method for determining a Fail Bit (FB) repair scheme includes: a bank to be repaired of a chip to be repaired is determined, the bank to be repaired including multiple target repair areas; initial repair processing is performed on an FB in each of the target repair areas using a redundant circuit; responsive to that a number of remaining Redundant Word Lines (RWLs) is greater than 0 and a number of remaining Redundant Bit Lines (RBLs) is greater than 0, a candidate repair sub-scheme for each target repair area is determined, and a candidate repair cost corresponding to each candidate repair sub-scheme is determined; and a target repair scheme for the bank to be repaired is determined according to respective candidate repair sub-schemes and candidate repair costs, where the target repair scheme corresponds to a minimum integrated repair cost.