Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Abstract: A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.

Abstract: A semiconductor process for removing oxide layers comprises the steps of providing a substrate having an isolation structure and a pad oxide layer, performing a dry cleaning process and a wet cleaning process to remove said pad oxide layer, forming a sacrificial oxide layer on said substrate, and performing an ion implantation process to form doped well regions on both sides of the isolation structure.

Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Abstract: A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.

Abstract: A process for forming a shallow trench isolation structure is provided. Firstly, a semiconductor substrate is provided. Then, a hard mask is formed over the semiconductor substrate, wherein the hard mask includes a pad oxide layer, a silicon nitride layer and an opening. Then, a trench is formed in the semiconductor substrate according to the opening Then, a pull-back process is performed to treat the silicon nitride layer at a sidewall of the opening, wherein the pull-back process is a wet etching process carried out in a phosphoric acid solution. After the pull-back process is performed, an insulating material is filled in the trench, thereby forming the shallow trench isolation structure.

Abstract: A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.

Abstract: A semiconductor process includes the following steps. A substrate is provided, which includes an isolation structure and an oxide layer. The isolation structure divides the substrate into a first region and a second region. The oxide layer is located on the surface of the first region and the second region. A dry cleaning process is performed to remove the oxide layer. A dielectric layer is formed on the first region and the second region. A wet etching process is performed to remove at least one of the dielectric layers located on the first region and the second region. A semiconductor structure is fabricated by the above semiconductor process.

Abstract: A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.

Abstract: A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench.

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract: A smart photovoltaic assembly and a photovoltaic system are provided. The smart photovoltaic assembly comprises a photovoltaic assembly main body, an installation plate disposed on a back surface of the photovoltaic assembly main body, and a current leading terminal connector provided on the installation plate for leading an electric current line from the photovoltaic assembly main body, wherein the current leading terminal connector has a first connector interface adapted for connecting with a second connector interface of a complementary electronic device. The current leading terminal connector is in electrical connection with the complementary electronic device by mutual connection of the first connector interface and the second connector interface. The photovoltaic system comprises the above mentioned smart photovoltaic assembly, wherein the electronic device may be a diode module, an electric voltage converting device, a monitor or other types of electronic devices according to the need of a user.

Abstract: The present invention discloses a photovoltaic module and a support thereof. The photovoltaic module comprises a photovoltaic cell laminate and a support adapted to be mounted onto an installation surface. The support is connected to a back surface of the photovoltaic cell laminate and comprises a first connecting portion close to a front side of the photovoltaic cell laminate and a second connecting portion disposed close to a back side of the photovoltaic cell laminate. When a plurality of photovoltaic modules is mounted onto the installation surface, the first connecting portion of one photovoltaic module is engaged with the second connecting portion of another adjacent photovoltaic module, so that a relative position of the photovoltaic module and another adjacent photovoltaic module is maintained and the plurality of photovoltaic modules is mounted onto the installation surface.

Abstract: The present invention discloses a wind deflector structure for a photovoltaic system and a photovoltaic system. The photovoltaic system comprises a photovoltaic module and a wind deflector structure. The photovoltaic module comprises a photovoltaic cell laminate and a support mounted onto the photovoltaic cell laminate. When the photovoltaic module is mounted onto an installation surface, a front side of the photovoltaic cell laminate is close to the installation surface and a back side thereof is far from the installation surface. The wind deflector structure is mounted close to the back side of the photovoltaic cell laminate and substantially shields a space between the back side of photovoltaic module and the installation surface. The wind deflector structure is fixed onto the supports of at least two photovoltaic modules side by side in a left-to-right direction so as to restrict a relative position of the at least two adjacent photovoltaic modules.