Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

Abstract: A switching power converter circuit comprises a single inductive circuit element; a common control loop circuit coupled to a circuit input and the inductive circuit element and including switching circuit elements to charge the inductive circuit element using energy provided at the circuit input; at least one current sensing circuit configured to sense inductor current of the inductive circuit element; one or more output control loop circuits that each include switching circuit elements activated to generate an output voltage; and one or more pulse width modulation (PWM) circuits configured to generate a PWM control signal to activate the switching circuit elements of the output control loop circuits and to change a peak voltage of the PWM control signal of the one or more PWM circuits according to the inductor current.

Abstract: Embodiments of the present disclosure describe frequency detection techniques for detecting power irregularities. These irregularities may include variations or abnormalities in switched-mode power supply circuit switching behavior, power spikes, and/or output oscillations. The frequency detection techniques may compare different frequency components of the power signal to detect irregularities.

Abstract: A switching power converter circuit comprises a single inductive circuit element; a common control loop circuit coupled to a circuit input and the inductive circuit element and including switching circuit elements to charge the inductive circuit element using energy provided at the circuit input; at least one current sensing circuit configured to sense inductor current of the inductive circuit element; one or more output control loop circuits that each include switching circuit elements activated to generate an output voltage; and one or more pulse width modulation (PWM) circuits configured to generate a PWM control signal to activate the switching circuit elements of the output control loop circuits and to change a peak voltage of the PWM control signal of the one or more PWM circuits according to the inductor current.

Abstract: Embodiments of the present disclosure describe frequency detection techniques for detecting power irregularities. These irregularities may include variations or abnormalities in switched-mode power supply circuit switching behavior, power spikes, and/or output oscillations. The frequency detection techniques may compare different frequency components of the power signal to detect irregularities.

Abstract: This disclosure describes techniques for controlling switching regulator switching operations. The techniques include selecting a given one of a plurality of clock signals based on a control signal. The techniques further include generating, by the switching regulator, an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals. The techniques further include varying the switching frequency of the switching regulator by changing a value of the control signal, used to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals that corresponds to the selected given one of the plurality of clock signals having respective values that correspond to respective ones of the plurality of refresh rate control signals.

Abstract: Techniques are provided for providing and maintaining an efficient deadtime for a switching circuit as the input voltage varies. In example, a switching circuit can include a control circuit configured to alternately switch the first switch and the second switch into and out of a low impedance state, and to prevent the first switch and the second switch from shorting the first supply rail with the second supply rail using a dead-time before a transition to the low impedance state of each of the first and second switches. The control circuit can a delay element that includes a compensation delay circuit configured to change in-kind with a change of a voltage difference between a first input supply rail and a second input supply rail of the switching circuit, and to limit a range of the dead-time over a range of the voltage difference.

Abstract: This disclosure describes techniques for controlling switching regulator switching operations. The techniques include selecting a given one of a plurality of clock signals based on a control signal. The techniques further include generating, by the switching regulator, an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals. The techniques further include varying the switching frequency of the switching regulator by changing a value of the control signal, used to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals that corresponds to the selected given one of the plurality of clock signals having respective values that correspond to respective ones of the plurality of refresh rate control signals.

Abstract: Techniques are provided for providing and maintaining an efficient deadtime for a switching circuit as the input voltage varies. In example, a switching circuit can include a control circuit configured to alternately switch the first switch and the second switch into and out of a low impedance state, and to prevent the first switch and the second switch from shorting the first supply rail with the second supply rail using a dead-time before a transition to the low impedance state of each of the first and second switches. The control circuit can a delay element that includes a compensation delay circuit configured to change in-kind with a change of a voltage difference between a first input supply rail and a second input supply rail of the switching circuit, and to limit a range of the dead-time over a range of the voltage difference.

Abstract: An electronic circuit includes parallel linear regulator circuits that support a range of different load currents. The electronic circuit includes a first linear regulator circuit coupled to an output node, a second linear regulator circuit coupled in parallel with the first linear regulator circuit and the output node, and a control circuit. The control circuit is configured to monitor the output node and to suppress or inhibit the second linear regulator circuit from supplying the output node when a representation of load power consumption is below a specified threshold. The first linear regulator circuit is configured to continue to supply a portion of the load power when the representation of load power consumption is above the specified threshold, and the control circuit may disable the second linear regulator circuit when the representation of load power consumption is below the specified threshold.

Abstract: An electronic circuit includes parallel linear regulator circuits that support a range of different load currents. The electronic circuit includes a first linear regulator circuit coupled to an output node, a second linear regulator circuit coupled in parallel with the first linear regulator circuit and the output node, and a control circuit. The control circuit is configured to monitor the output node and to suppress or inhibit the second linear regulator circuit from supplying the output node when a representation of load power consumption is below a specified threshold. The first linear regulator circuit is configured to continue to supply a portion of the load power when the representation of load power consumption is above the specified threshold, and the control circuit may disable the second linear regulator circuit when the representation of load power consumption is below the specified threshold.