Abstract: A digital controlled oscillator (14) generates an oscillator clock that is phase locked to a reference clock. A control circuit (12) generates a reset signal from the reference clock that sets the edges of the oscillator signal in line with an edge of the reference clock. The reset signal must have correct timing and duration. A course tune detector (16, 18) monitors the oscillator clock and generates course tune control signals (CT) that adjust the reset signal pulse width and the oscillator signal frequency by adding and removing capacitors from the inverters in the control circuit and digital controlled oscillator. A phase comparator (22) compares the reference clock and the oscillator clock. A fine tune detector (20) monitors the phase comparison and generates fine tune control signals (FT) that make fine adjustments to the pulse width of the reset signal and the frequency of the oscillator signal.

Abstract: A bias voltage for a VCO is generated by monitoring UP and DOWN control signals from a charge pump and generating first and second output signals upon detecting a predetermined number of consecutive UP pulses or DOWN pulses. The first output signal causes a shift register pre-loaded with a data pattern having one odd logic state to shift one bit location to left, while the second output signal moves the odd logic state one bit location to the right. The bias voltage to the VCO is selected based on the odd logic state bit location. Any variation in VCO output frequency due to intermittent ground bounce is eliminated by requiring a consecutive number of UP pulses or DOWN pulses before moving the VCO bias point.

Abstract: A digital clock circuit generates a high-speed clock and window pulses substantially centered about transitions of the high-speed clock in one quadrant of an integrated circuit (IC) and routes the high-speed clock and window pulses to other quadrants of the IC where a low-speed clock generator develops a low-speed clock signal from the window pulses. A control circuit checks alignment between the high-speed and low-speed clock signals and adjusts first and second shift registers to control the delay in generating the low-speed clock as necessary to maintain alignment. The first shift register controls the falling edge of the low-speed clock signal and the second shift register controls the rising edge of the low-speed clock signal.

Abstract: A voltage controlled oscillator runs at full speed to generate an output frequency dependent on temperature and process variation. First and second clock signals are generated from the oscillator signal, while third and fourth clock signals are developed in response to an input clock signal. The number of clock signals occurring during a first state of the third clock signal are counted for providing a plurality of output signals also indicative of the temperature and process variation. The plurality of output signals compensate an input signal for the temperature and process variation for providing an output signal.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. A programmable divider latches a program integer for providing a latch integer, compares the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal when the first and second digital input signals have a first logic state at a first transition of a control signal and a second logic state at a second transition of the control signal. One false lock triggers an out-of-phase status indicator. The lock detection signal must return to a valid state for a predetermined number of periods before the phase lock status indicates a valid lock condition. The first and second digital input signals may operate with a non-50% duty cycle.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signal are applied to a lock detection circuit for generating a first digital output signal having a first logic state from a mutually exclusive combination of the first and second digital signals. The first logic state of the first digital output signal is compared with a time slot window formed by a control signal for generating a true lock detection signal when the first logic state of the first digital output signal occurs within the time slot window and a false lock detection signal when the first logic state of the first digital output signal occurs outside the time slot window.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A power on reset circuit uses a first inverter with hysteresis operating in response to a first power supply potential to develop a first reset signal when the first power supply potential is greater than a first predetermined threshold. A second inverter with hysteresis also operates in response to the first power supply potential for developing a second reset signal when the first power supply potential is greater than a second predetermined threshold. The first reset signal disables the second inverter until the first power supply potential reaches the first predetermined threshold. A delay circuit delays the second reset signal to ensure the first power supply potential is fully operational before indicating a ready condition.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A clock alignment circuit is responsive to a high speed clock signal for generating a low speed clock signal. A clock generator circuit monitors the phase difference between the high speed clock signal and the low speed clock signal and develops a control signal in response thereto during a time slot window signal for adjusting the transitions of the low speed clock signal to align with the high speed clock signal. The clock generator circuit is placed in the vicinity of the associated utilization circuit to that the low speed and high speed clock signals maintain alignment.

Abstract: A programmable logic array operates with a single clock signal frequency which delays a control signal allowing time for the input signals to reach steady state on the column conductors of the AND-plane before enabling an active pull-up circuit to latch those column conductors left floating by the input signals. The control signal for the active pull-up circuit of the OR-plane is also delayed allowing time for the signals on the column conductors and row conductors of the OR-plane to reach steady state and provide glitch-free output signals. The propagation paths for the control signals are made slower than the worst case data path through the AND-plane and OR-plane to eliminate race conditions.

Abstract: A voltage controlled oscillator (VCO) includes a voltage controlled load. The voltage controlled load supplies additional capacitive loading to the VCO, via a transmission gate, at low frequencies to decrease the frequency-gain factor of the VCO. Moreover, at high frequencies, the effect of the voltage controlled load is minimized by turning off the transmission gate thereby allowing the VCO to operate at maximum frequency for worst case speed conditions.

Abstract: A voltage controlled oscillator (VCO) generates a 50% duty cycle clock. The 50% duty cycle clock is derived directly from the operating frequency of the VCO thereby abating the need for the VCO to operate at twice the desired clock frequency. This allows the VCO to be utilized in high frequency phase-locked loop systems.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit is provided which accepts Transistor-Transistor Lock (TTL) input signal levels without generating any significant DC current path. A reference voltage circuit (1, FIG. 1) provides first and second reference voltages (V.sub.A and V.sub.B, FIG. 1) which are coupled to first and second stages, respectively, of the input buffer circuit (3, FIG. 1), and which are of predetermined magnitudes and scaled relative to each other to permit the P-channel devices of the input buffer circuit to turn off completely when the input to the circuit is "high", while allowing a successively higher output at each successive stage of the input buffer circuit. The reference circuit 1 is compensated for power supply and process window variations.

Abstract: A driver circuit directly couples the clock signal to gate electrodes of pull-up devices to minimize the loading effect on the clock signal. The pull-up devices pull up the output to substantially the positive power supply voltage. The clock signal is coupled to the gate electrodes of the pull-up devices by a transistor whose gate electrode is controlled by a control signal. The control signal also triggers the pull down of the gate electrode of the pull-up devices when it is not desired to couple the clock signal to the gate electrode of the pull-up devices.

Abstract: An active pull-up circuit is provided which is process compensating. The active pull-up circuit contains a voltage reference which drives a source follower. The inverting output of the source follower controls a pull-up device which is in parallel with an active pull-up device. The active pull-up device can be much smaller in size since it is now assisted by the controlled pull-up device. The controlled pull-up device is held off until the active pull-up device pulls up the bus or line connected to the active pull-up circuit to a predetermined voltage level.