Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.

Abstract: A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.

Abstract: A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted.

Abstract: A new method of metal plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing and metal residues after CMP is described. An oxide layer is provided overlying semiconductor device structures in and on a semiconductor substrate. A sacrificial high polishing rate (HPR) layer is deposited overlying the oxide layer. An opening is etched through the HPR layer and the oxide layer to one of the semiconductor device structures. A barrier layer and a metal layer are deposited over the surface of the HPR layer and within the opening. The metal layer, barrier layer, and HPR layer overlying the oxide layer are polished away by CMP. The polishing rate of the HPR layer is higher than that of the metal layer with the result that after the HPR layer is completely removed, the metal layer remaining within the opening has a convex shape. The oxide layer is over-polished until endpoint detection is received.

Abstract: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply.

Abstract: A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a “holes everywhere” or a “reverse metal holes” mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.

Abstract: A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti.

Abstract: A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light.

Abstract: A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

Abstract: Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed.

Abstract: A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack.

Abstract: In one embodiment, a masking chuck (68) is placed in contact with an integrated circuit structure (70) that contains conductive members (90). The masking chuck (68) is used to deposit a dielectric layer (92) on the integrated circuit structure (70). The dielectric layer (92) is then cured, and the masking chuck (68) is separated from the integrated circuit structure (68) to define openings (96) within the dielectric layer (92) which expose a portion of the underlying conductive members (90). A conductive layer (100) is then deposited in the openings (96), and polished to form conductive members (102) within the openings (96), which are electrically shorted to the underlying conductive members (90).

Abstract: A method of forming shallow trench isolation trenches for use with borderless contacts is achieved. A silicon nitride layer protects the shallow trench oxide layer from overetch damage. A silicon substrate is provided. A pad oxide layer is grown. A polishing stop layer, of polysilicon or silicon nitride, is deposited. The polishing stop layer, pad oxide layer, and silicon substrate are patterned to form the shallow trenches. A trench oxide layer is deposited to fill the shallow trenches. The trench oxide layer is polished down with the polishing stop layer as a polishing stop. The trench oxide layer is etched down to a level below that of the pad oxide layer. A silicon nitride layer is deposited. A polishing layer of oxide is deposited. The polishing layer and the silicon nitride layer are polished down with the polishing stop layer as a polishing stop. The polishing stop layer is etched away. The silicon nitride layer is etched to remove vertical sidewalls.

Abstract: A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings.

Abstract: A flexible road safety-guard is provided. The road safety-guard has a base 1, an upright column 2, a safety-guard 3 and connectors. The base 1 is positioned at the lower end of the upright column 2 forming an integrated whole therewith. Mounting holes are provided in the safety-guard. Each of the upright column, the base and the safety-guard is made of Rotational Grade Polyethylene material by slush molding and has hollow structure. Male and female die block interfaces are formed respectively at each end of the safety-guard along its length, that is, one end is an insert interface having smaller outer profile and the other end is a mating interface which engages with the insert interface. The safety-guard 3 has a cross-sectional shape which is substantially flat on one side and contoured on an opposite side, the contoured side having vertically spaced arcuate portions interconnected by a flattened portion.

Abstract: A new method for planarizing silicon dioxide surfaces in semiconductor structures. Starting with a structure of an underlying layer (for instance a layer of metal lines) a layer of oxide is deposited and profiled by positive tone imaging. A layer of PPMS is deposited. Using the mask of the starting structure, the PPMS layer is exposed changing the PPMS to PPMSO in the exposed regions. The unexposed PPMS is removed, the PPMSO (unexposed regions of the PPMS) are planarized, this planarization can proceed to the point where no more PPMSO is present (the PPMSO “columns” are removed together with the intra-layer of patterned oxide). The surface thus created shows excellent planarity, this surface can be further planarized down to the top level of the underlying pattern, if it is desirable to do so.

Abstract: An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug.

Abstract: A method of forming trenches having different depths for use in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing stop of silicon nitride is deposited. An oxide layer is grown overlying the silicon substrate. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned first trenches. A polysilicon layer is deposited overlying the oxide layer and filling the openings for the planned first trenches. The polysilicon layer is polished down to the top surface of the oxide layer such that the polysilicon layer remains only in the openings of the planned first trenches. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned second trenches.

Abstract: A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.