Patents by Inventor Lap Keung Chow

Lap Keung Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7439099
    Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: October 21, 2008
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang, William Lap Keung Chow
  • Patent number: 6982491
    Abstract: A process for fabricating an integrated circuit package includes: providing a substrate having conductive traces therein, the substrate including a cavity therein; mounting a semiconductor die to a first surface of the substrate, in a flip-chip orientation such that a sensor portion of the semiconductor die is aligned with the cavity and conductive interconnects connect pads of the semiconductor die to the conductive traces of the substrate; filling an area surrounding the interconnects with an underfill material; and mounting a plurality of conductive balls on the first surface of the substrate and in electrical connection with the conductive traces such that ones of the conductive balls are connected to ones of the pads of the semiconductor die via the conductive traces.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: January 3, 2006
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Sadak Thamby Labeeb, Lap Keung Chow
  • Patent number: 6841859
    Abstract: A process for fabricating a cavity-type integrated circuit package. The process includes: supporting an interior portion of each of a plurality of leads, in a mold; supporting a die attach pad in said mold; molding a package body in said mold such that said leads extend from an interior cavity of said package body to an exterior thereof; mounting a semiconductor die to said die attach pad; wire bonding various ones of said leads to said semiconductor die; adding a fill material for covering at least a surface of said interior portion of said leads; and mounting a lid on said package body for enclosing said die in said cavity of said package body.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 11, 2005
    Assignee: Asat Ltd.
    Inventors: Labeeb Sadak Thamby, Neil McLellan, Hugo Chi Wai Wong, William Lap Keung Chow
  • Patent number: 6821817
    Abstract: A process for fabricating a cavity-type integrated circuit package. The process includes: supporting an interior portion of each of a plurality of leads, in a mold; supporting a die attach pad in said mold; molding a package body in said mold such that said leads extend from an interior cavity of said package body to an exterior thereof; mounting a semiconductor die to said die attach pad; wire bonding various ones of said leads to said semiconductor die; adding a fill material for covering at least a surface of said interior portion of said leads; and mounting a lid on said package body for enclosing said die in said cavity of said package body.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: November 23, 2004
    Assignee: ASAT Ltd.
    Inventors: Labeeb Sadak Thamby, Neil McLellan, Hugo Chi Wai Wong, William Lap Keung Chow
  • Patent number: 6781242
    Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: August 24, 2004
    Assignee: ASAT, Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang, William Lap Keung Chow