Abstract: Processing an audio signal is disclosed. A source audio signal to be rendered by a touch input medium is received. An indication of an event where the touch input medium has been contacted at a location on the touch input medium such that rendering of the source audio signal by the touch input medium is affected by the contact is received. At least a portion of the source audio signal is modified based on an expected effect of the contact on the touch input medium determined using the indication of the detector.

Abstract: A touch input detector is disclosed. The touch input detector includes an acoustic transmitter for transmitting an acoustic wave across a touch input medium. The touch input detector also includes an acoustic receiver for receiving the transmitted acoustic wave, wherein the timing of the incidence of the acoustic wave on the acoustic receiver indicates at least a portion of a touch input location on a surface of the touch input medium. The touch input detector further includes an acoustic dampening material coupled to the touch input medium to dampen reflections of the transmitted acoustic wave.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an upconverted signal in response to an input signal and a first oscillation signal. The second circuit may be configured to generate a downconverted signal in response to the upconverted signal and as second oscillation signal. The third circuit may be configured to generate an output signal in response to the downconverted signal and a third oscillation signal derived from the second oscillation signal. The upconverting and downconverting may filter undesired channels from the output signal.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to filter an analog input signal in an analog domain in response to one or more control signals. The second circuit may be configured to convert the analog input signal to a digital signal. The third circuit may be configured to generate the control signals in response to the digital signal. The third circuit may also be configured to control skewing of the analog input signal within the first circuit to partially compensate for frequency dependent effects associated with a transmission medium.

Abstract: An apparatus comprising an amplifier, a first resistor and a second resistor. The amplifier (i) comprises a first transistor and a second transistor and (ii) may be configured to generate an output signal in response to an input signal. The first resistor may be connected between an emitter of the second transistor and a signal ground. The second resistor may be connected between the emitter of the second transistor and a base of the first transistor. A gain of the amplifier may be adjusted by varying a value of the first resistor and a value of the second resistor.

Abstract: An apparatus comprising a first calibration circuit and a phase shift network stage. The first calibration circuit may be configured to generate a control signal. The phase shift network stage may comprise one or more tunable phase shift elements and be configured to provide a tunable impedance. The phase shift network stage may be tuned in response to the control signal and a conductance of the tunable phase shift elements.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises one or more master amplifiers and a plurality of control amplifiers. The first circuit may be configured to generate a plurality of control signals in response to (i) a first signal related to a desired gain and (ii) a second signal related to a known reference. The second circuit may be configured to generate an output signal in response to (i) an input signal and (ii) the plurality of control signals. The output signal may be amplified with respect to the input signal.

Abstract: A digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which integrates the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors store a binary representation of the digital input signal. The output circuit includes a zeroth order sample-and-hold circuit having first and second stages with respective first and second operational amplifiers. The first and second stages are cascaded together during a sample phase so that the analog output signal is stored in a capacitor in a feedback path between the output of the second stage and the input of the first stage, and are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.