Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A plate line segmentation scheme for a 1T/1C ferroelectric memory architecture includes an array of 1T/1C ferroelectric memory cells, word lines corresponding to each row of 1T/1C ferroelectric memory cells, and plate lines corresponding to each row of 1T/1C ferroelectric memory cells, wherein each plate line is divided into two or more equal plate line segments, only one of which is driven when a corresponding word line is selected.

Abstract: A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

Abstract: A sense amplifier cell layout for use in a 1T/1C ferroelectric memory array includes a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal and a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal, wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

Abstract: A reference cell for a 1T/1C ferroelectric memory includes a transistor of a first polarity type having a gate coupled to a reference cell word line, and a current path coupled between a bit line and an internal reference cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line, and a current path coupled between a source of supply voltage and the internal reference cell node, and a ferroelectric capacitor coupled between the internal reference cell node and ground.

Abstract: A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.

Abstract: A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.