Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.

Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.

Abstract: Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

Abstract: A signal synchronization mapper for mapping an input data stream characterized by a first frequency (typically a SONET/SDH stream) into an output data stream characterized by a second frequency. A phase lock control loop containing a “delta-sigma” (&Dgr;-&Sgr;) modulator which functions as a voltage controller oscillator synchronizes the data rate of the output stream to that of the input stream in a manner which simplifies attenuation of jitter energy when the output data stream is desynchronized (demapped). The modulator generates an accurate pulse train by duty-cycle dithered modulation of the input stream, which the mapper interprets as stuff/nullide-stuff commands such that the mapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time) thus allowing utilization of a FIFO buffer without the need to monitor the buffer's depth or its pointers.

Abstract: A digital delay line, which includes a plurality of multiplexer delay elements, arranged in sequence with each of the plurality of multiplexer delay elements having an associated control input. A clock signal line is coupled to a clock input of each of the plurality of multiplexers and is operative to provide synchronous, phase aligned clock signals from a clock signal source to each of said clock inputs. A control input is coupled to each of the plurality of multiplexer delay elements and is operative to transmit to each of the plurality of multiplexer delay elements an associated control signal. In response to a first change in the control signal an associated delay element is added to the delay line and in response to a second change the delay element is removed from the delay line.

Abstract: A digital delay line, which includes a plurality of multiplexer delay elements, arranged in sequence with each of the plurality of multiplexer delay elements having an associated control input. A clock signal line is coupled to a clock input of each of the plurality of multiplexers and is operative to provide synchronous, phase aligned clock signals from a clock signal source to each of said clock inputs. A control input is coupled to each of the plurality of multiplexer delay elements and is operative to transmit to each of the plurality of multiplexer delay elements an associated control signal. In response to a first change in the control signal an associated delay element is added to the delay line and in response to a second change the delay element is removed from the delay line.

Abstract: A parallel to serial converter comprising a parallel word latch for receiving a series of words comprised of parallel data words, a shift register for receiving the parallel data words and for storing bits of a parallel data word in a series of shift register stages upon receipt of a first enable signal, and for providing a serial stream of bits at a serial clock rate, a circuit for receiving a serial clock signal and for providing the serial clock signal to the shift register to enable shifting of the stored bits to an output as the serial stream of bits, and a controller for generating the enable signal and for applying the enable signal to the shift register and parallel word latch, said controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A plurality of data streams time-division multiplexed into a single stream are concurrently processed. State vectors characteristic of each data stream are stored in unique read-write memory locations having known addresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved.