Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

Abstract: Methods, devices, and systems relating to Serial Attached SCSI (SAS) storage interconnect technology are provided. An SAS serial connection is established between an SAS initiator and an SAS expander over a physical link for communications between the SAS initiator and a plurality of target devices. The plurality of target devices is in communication with the SAS expander. SAS packets associated with each of the plurality of target devices are dynamically multiplexed and transmitted over the single SAS serial connection. Each SAS packet comprises one or more information bits indicating the target device with which the SAS packet is associated. The dynamically multiplexed SAS packets transmitted over the SAS connection may comprise SAS packets associated with at least two target devices having different maximum physical link rates. A result may be improved bandwidth utilization of the physical link when legacy SAS target devices with slower physical link rates are utilized.

Abstract: Methods, devices, and systems relating to Serial Attached SCSI (SAS) storage interconnect technology are provided. An SAS serial connection is established between an SAS initiator and an SAS expander over a physical link for communications between the SAS initiator and a plurality of target devices. The plurality of target devices is in communication with the SAS expander. SAS packets associated with each of the plurality of target devices are dynamically multiplexed and transmitted over the single SAS serial connection. Each SAS packet comprises one or more information bits indicating the target device with which the SAS packet is associated. The dynamically multiplexed SAS packets transmitted over the SAS connection may comprise SAS packets associated with at least two target devices having different maximum physical link rates. A result may be improved bandwidth utilization of the physical link when legacy SAS target devices with slower physical link rates are utilized.

Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: A data integrity (DI) protection circuit and method provide overlapping DI protection without increasing memory requirements. Write data parity is checked after write data error correcting code (ECC) check bits are generated, which is stored with the write data in memory without storing the write data parity. A corrupt location cache stores the write address and a write response error is generated when a write data parity error or write address parity error is detected. Read data and read data ECC check bits retrieved from the memory are checked and single bit errors are corrected, while double-bit errors result in a read error response. Read data parity is generated, and the corrected read data and corrected read data ECC check bits are then checked for bit errors. The corrupt location cache is searched for the read address, and a cache hit results in a read error response.

Abstract: Provided is an apparatus and method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol. A SAS-PCIe bridge includes a SAS component configured to communicate with a SAS device in a SAS domain and a PCIe component configured to communicate with a PCIe switch in a PCIe domain. The SAS component and the PCIe component are configured to convert data between the SAS protocol and the PCIe protocol.

Abstract: SAS/SATA Store-Forward (SSSF) buffering enables SAS/SATA block storage devices capable of slower physical link rates to transfer data at a SAS topology data rate. 6 Gbps SAS and SATA disk drives can exchange data at 12 Gbps with 12 Gbps hosts through 12 Gbps SAS expanders employing an SSSF device. The SSSF device improves data transfer performance in the storage area network by optimizing host-side link utilization. The device includes a host-side interface communicating with the host at a host-side rate, a drive-side interface communicating with the target at a drive-side rate equal to or less than the host-side rate, a buffer receiving SAS frames or SATA FIS's, and control logic to control communication between the host-side interface and buffer at the host-side rate and between the drive-side interface and the buffer at the drive-side rate.

Abstract: A system and method for providing redundant access paths to a storage device make use of a processor to analyze instructions received from hosts to allow for command queuing, host switching, and command replacement where necessary. The system allows for either Serially Attached SCSI or Serial ATA hard drives to be connected to the same topology and to require no host intervention on the coordination of drive access in a multi-host environment. A single ported SATA device can then appear multi-ported and can support a redundant architecture within a SAS topology.

Abstract: Broadcast primitive filtering in a SAS expander using virtual domains. The virtual domains can be non-overlapping or overlapping logical subsets of the physical topology, or a logical construct based on the membership of a device within a group. Broadcast event propagation is handled in accordance with predetermined policies associated with the virtual domains. These policies can, for example, include limiting the broadcast traffic within the boundaries of the logical zones defined by the subsets, or routing the broadcast events in accordance with access policies, or privileges, associated with the group.

Abstract: A method and system are provided for broadcast message filtering in SAS expanders. Common SAS topology defined by ANSI T10 specification only supports spanning tree topology (without loops) interconnection among multiple end devices and expander devices. Broadcast message filtering provides a mechanism to selectively discard broadcast messages, or primitives, in the SAS expanders to break the infinite loop path that broadcast primitives can traverse. This enables new SAS physical topologies with loops that are otherwise difficult or impossible to realize using SAS expanders that handle primitive broadcasts according to the definition of the SAS standard. By allowing redundant paths in a SAS topology, the problem of infinite broadcast flooding in SAS topology is reduced. Selectively forwarding broadcast messages can be based on whether the broadcast was originated at the source phy, or received by the source phy, or based on whether the source phy is a filtered phy.

Abstract: A method and apparatus for determining a set of common link rates for communication between two storage network elements in a storage network system. During the speed negotiation process, a controlling storage network element receives supported link rate information from a connected storage network element without providing any information in return. By not providing such information, although the speed negotiation process may not be completed, the controlling storage network element is still able to determine the supported link rates of the connected storage network element.

Abstract: A multi-port switch and a method of command switching using such a switch. Multiple virtual targets provide multiple hosts with access to the physical target device attached to the target interface of the switch. The switch intelligently dispatches operations received by the virtual targets to the physical storage target device to provide shared access. In doing so, the communication between the switch and the physical target can fully comply with the SATA protocol without the physical target being aware that the operations have originated from multiple physical hosts, and without the multiple physical hosts being aware of the shared nature of the physical SATA target device.

Abstract: A method and apparatus are provided for routing in an SAS expander for logical zoning. Common SAS topology defined by the ANSI T10 specification only relates to physical topology with multiple end devices, as well as to expander devices and the broadcast handling mechanisms in such physical topologies. The present invention introduces the concept of virtual topologies that can be non-overlapping or overlapping subsets of the physical topology and the routing mechanism that handles the routing issues with the virtual topologies.

Abstract: A method and apparatus are provided for controlling the powering-up or spin-up of devices such as hard drives using expanders in a SAS topology. The method and apparatus provides a mechanism to coordinate spin-up control among a topology of expanders. The present invention enables an expander to both process the reception of the NOTIFY command to spin up attached devices and to propagate such command to further expanders. Hierarchical spin-up control provides an advantageous, in-band mechanism that controls the expanders within the topology to limit the total number of devices powering-up at any given time.

Abstract: A Forward Propagation Architecture is a novel switch architecture based on well-known unicast switching architectures, and provides two desirable properties: (1) no rearrangement of established calls is ever required and (2) the architecture is strictly non-blocking for multicast, even when multicast destinations are dynamically added to existing calls. These properties (excluding dynamic multicast destination addition) can be provided by standard architectures or Time:Space:Time architectures with speedup proportional to the width of the widest multicast to be supported. The speedup required by the FPA is constant and practical (approximately 4× speedup) and at significantly less hardware cost than n2 architectures. The key to the FPA's capability is a sequentially doubled fabric with a feedback loop. The FPA requires a routing algorithm for connection setting. The connection-setting algorithm is sufficiently simple to be implemented in hardware.

Abstract: A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof.

Abstract: A multi-channel network device for interfacing between a plurality of physical data links and a control processor, where each physical data link is characterized by a data stream of data packets communicated according to a data link control protocol. The multi-channel network device includes a plurality of receive-side line interfaces, with each with each receive-side line interface having at least one channel associated therewith. Each receive-side line interface is operative to receive incoming data packets from one of the physical data links such that each incoming data packet is received in at least one incoming data segment. Each receive-side line interface is also operative to determine a time-slot number for each incoming data segment arriving thereon.

Abstract: A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.