Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. One specific embodiment is directed to a new video decoder which decodes portions of a single image, e.g., frame, at different resolutions. Areas of the image along high contrast vertical or horizontal edges are decoded at full resolution while other portions of the same image are decoded at reduced resolution. By decoding and storing portions of reduced resolution images at full resolution for reference purposes, the risk of prediction errors resulting from the use of downsampling on reference frames is reduced.

Abstract: Methods and apparatus for encoding image data to facilitate subsequent insertion of local image data. Also methods and apparatus for inserting image data, e.g., at local broadcast stations, without having to fully decode a received encoded bitstream. The encoding methods involve treating images to be encoded as a plurality of distinct, non-overlapping image regions or segments for encoding purposes. Image segments which are designated for use for local data insertion are not used as reference data for motion compensated prediction purposes when generating motion vectors to represent image areas, e.g., the area representing the main picture, which are outside the local data insertion segments. Because image segments which may be replaced are not used as reference data for image segments which will not be replaced, unintentional prediction errors which might otherwise result from replacing one or more image segments as part of a local data insertion operation are avoided.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for simulating, in reduced resolution video decoders, the biasing effect associated with MPEG's specified rounding of pixel values including a fractional component of 0.5 to the next highest integer value are described. In one embodiment, the biasing effect is simulated by generating luminance and chrominance DC DCT coefficient bias values from, e.g., motion vector offset data. The DC DCT bias values are then added to the DC DCT coefficients of the luminance and chrominance blocks, respectively, which correspond to the same image block to which the motion vector data used to generate the bias values corresponds. In another embodiment, pixel values are directly adjusted to simulate the biasing effect associated with MPEG compliant rounding. In such an embodiment, luminance and chrominance pixel biasing values are generated as a function of, e.g., motion vector offset information. The bias values are added to the pixel values generated through the use of motion compensated prediction.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for encoding, decoding and displaying images in a manner that provides for relatively smooth motion are described. In accordance with the invention a multi-sync display device is used and the refresh rate of the display device is controlled to minimize or avoid judder. Control of the display device refresh rate is performed in various embodiments, as a function of frame display, frame coding, field coding and/or image capture rate information included in an encoded bitstream. Alternatively, the refresh rate of a display is controlled as a function of decoding rate information or other information available from a decoder. In one exemplary embodiment, frames are displayed and the refresh rate of a display device is controlled to be an integral multiple of the indicated frame display rate included in an encoded bitstream.

Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. One specific embodiment is directed to a new video decoder which decodes portions of a single image, e.g., frame, at different resolutions. Areas of the image along high contrast vertical or horizontal edges are decoded at full resolution while other portions of the same image are decoded at reduced resolution. By decoding and storing portions of reduced resolution images at full resolution for reference purposes, the risk of prediction errors resulting from the use of downsampling on reference frames is reduced.

Abstract: Methods and apparatus for implementing video decoders at a reduced cost are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying the complexity of image enhancement operations, e.g., prediction filtering operations, as a function of whether luminance or chrominance data is being processed. In order to reduce data storage requirements, luminance and chrominance data corresponding to previously encoded images may be stored at different resolutions with, in some embodiments, chrominance data being stored at less than half the resolution of luminance data. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques.

Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. In particular, techniques for identifying blocks of pixels, referred to as constant block regions, having approximately the same intensity in terms of luminance values, are discussed. High contrast vertical and/or horizontal edges will cause significant prediction errors in images generated by reduced resolution decoders under certain conditions. Methods for assessing when such conditions exist and a significant prediction error is likely to occur are described. In addition methods and apparatus for minimizing the effect of such prediction errors in downsampling decoders are also described.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. In particular, techniques for identifying blocks of pixels, referred to as constant block regions, having approximately the same intensity in terms of luminance values, are discussed. High contrast vertical and/or horizontal edges will cause significant prediction errors in images generated by reduced resolution decoders under certain conditions. Methods for assessing when such conditions exist and a significant prediction error is likely to occur are described. In addition methods and apparatus for minimizing the effect of such prediction errors in downsampling decoders are also described.

Abstract: Methods and apparatus for implementing video decoders at a reduced cost are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying the complexity of image enhancement operations, e.g., prediction filtering operations, as a function of whether luminance or chrominance data is being processed. In order to reduce data storage requirements, luminance and chrominance data corresponding to previously encoded images may be stored at different resolutions with, in some embodiments, chrominance data being stored at less than half the resolution of luminance data. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques.

Abstract: Methods and apparatus for combining linear image post-processing operations with an inverse discrete cosine transform (IDCT) operation are described. In accordance with various embodiments of the present invention IDCT and downsampling operations are combined into a single operation to achieve the same image processing result as sequential IDCT and downsampling operations. By combining the two operations and performing downsampling in the DCT, as opposed to pixel domain, significant complexity reduction is achieved over embodiments where the two operations are performed sequentially. In one particular embodiment, when interlaced images are being processed, combined IDCT/downsampling circuits which perform field based, as opposed to frame based, downsampling in the DCT domain are employed. The method and apparatus of the present invention can be used to implement circuits which perform a combined full order IDCT/downsampling operation and/or a reduced complexity combined full order IDCT/downsampling operation.

Abstract: An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data.

Abstract: Methods and apparatus for implementing video decoders at a lower cost than known video decoders are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying prediction filter complexity as a function of whether luminance or chrominance data is being processed. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques. The decoded I and P frame data is stored for use when making subsequent predictions if required.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.