Abstract: A dedicated context cycling microprocessor which features a plurality of input/output circuits for receiving and transmitting information and an individual set of dedicated on-board resources for each plurality of processing contexts. A distinct processing context is provided for each of a plurality of the input/output circuits, and a timed context is also provided for concurrently scheduling multiple processing contexts and enforcing time constraints associated with this schedule. The timed context has a pseudo-queue list which represents an ordered set of data parameters and program memory addresses for scheduling each of the processing contexts. The dedicated on-board resources include a plurality of registers for each of the processing contexts, such as at least one general purpose register and a program counter. A multiplexer circuit is also provided for moving data between the input/output circuits, the dedicated registers of the processing contexts and the computational unit.

Abstract: A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus.

Abstract: An extended Harvard architecture memory system which features an address store for containing an ordered sequence of program memory addresses, and a value store for containing a series of related data value sets. Each of the addresses contained in the address store is associated with a distinct set of instructions, such as a subroutine, that is contained in the program memory. The address store may also contain the address of one or more instruction arguments that are, in turn, contained in the value store or in a separate data memory. Both the address store and the value store are preferably connected to the same data communication path which is used by the data memory of the computer. The value store also includes a logic interface for enabling a plurality of different address increments to be programmably selected.