Patents by Inventor Larry Buffle

Larry Buffle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162280
    Abstract: An electrical device for high-voltage applications and a method for obtaining an electrical device. The electrical device includes a capacitor having: a bottom electrode having a conductive structure, the conductive structure including a base surface and facing protruding walls extending upwards and having a highest surface; a top electrode having at least one conductive region arranged between the facing protruding walls and having a top surface, wherein the top surface of the at least one conductive region lies below or at the level of the highest surface of the protruding walls; and a dielectric region extending conformally over the bottom electrode and surrounding the top electrode, the capacitor being formed by the bottom and top electrodes separated by the dielectric region.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Inventors: Larry BUFFLE, Frédéric VOIRON
  • Patent number: 11955568
    Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 9, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Larry Buffle, Frédéric Voiron, Sophie Archambault
  • Publication number: 20230245834
    Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Inventors: Larry BUFFLE, Frédéric VOIRON, Julien EL SABAHY, Brigitte SOULIER
  • Publication number: 20230134193
    Abstract: An electronic component comprising a 3D capacitive structure includes a substrate having a contoured surface comprising a plurality of wells extending from the surface into the substrate body, a dielectric formed over, and conforming to the shape of, the contoured surface, and a first electrode formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes a second electrode and the dielectric is interposed between it and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and contact an insulating layer formed under the substrate, reducing the electrostatic field arising in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The openings at the bottom of the wells are obturated by the dielectric, defining blind holes within the wells, and the first electrode is in the blind holes.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 4, 2023
    Inventors: Larry BUFFLE, Frédéric VOIRON
  • Publication number: 20230125974
    Abstract: A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventors: Julien EL SABAHY, Larry BUFFLE, Stéphane BOUVIER, Frédéric VOIRON
  • Publication number: 20220392852
    Abstract: A semi-conductor structure with a crack-blocking three-dimensional structure is described. The semiconductor structure includes a substrate; a functional circuit structure disposed in an area of the substrate; and a three-dimensional structure having at least one continuous trench that extends perpendicularly towards a base surface of the substrate and that surrounds the area of the substrate containing the functional circuit structure.
    Type: Application
    Filed: August 17, 2022
    Publication date: December 8, 2022
    Inventors: Frédéric VOIRON, Larry BUFFLE
  • Publication number: 20220393038
    Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 8, 2022
    Inventors: Larry BUFFLE, Frédéric VOIRON, Sophie ARCHAMBAULT
  • Publication number: 20210327867
    Abstract: RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Stéphane Bouvier, Larry Buffle, Sophie Gaborieau
  • Publication number: 20210091174
    Abstract: A semiconductor structure that includes a protruding wall structure that extends from a base surface of a substrate. Corners of the protruding wall structure may be smoothed or rounded to reduce electrical stress within the structure. The protruding wall structure may be partitioned into multiple wall regions disposed along different directions of the substrate to reduce mechanical stress.
    Type: Application
    Filed: December 10, 2020
    Publication date: March 25, 2021
    Inventors: Frédéric Voiron, Larry Buffle