Abstract: An electrical device and a method for manufacturing thereof. The electrical device comprises a capacitor including a porous structure, the porous structure comprising: a first electrode region comprising first pores, wherein these first pores comprise first conductive wires; a second electrode region comprising second pores, wherein these second pores comprise second conductive wires; and a dielectric region comprising third pores and interposed between the first and second electrode regions, wherein the capacitor is formed by the first pores of the first electrode region and the second pores of the second electrode region facing each other and being separated by the third pores of the dielectric region.

Abstract: An electrical device for high-voltage applications and a method for obtaining an electrical device. The electrical device includes a capacitor having: a bottom electrode having a conductive structure, the conductive structure including a base surface and facing protruding walls extending upwards and having a highest surface; a top electrode having at least one conductive region arranged between the facing protruding walls and having a top surface, wherein the top surface of the at least one conductive region lies below or at the level of the highest surface of the protruding walls; and a dielectric region extending conformally over the bottom electrode and surrounding the top electrode, the capacitor being formed by the bottom and top electrodes separated by the dielectric region.

Abstract: A method of manufacturing an integrated electrical device comprising an energy storage component, that includes: providing a support comprising a porous region; forming an insulating layer having an opening delimiting a portion of the porous region; forming a bottom electrode layer; etching the bottom electrode layer such that the bottom electrode layer is removed on the insulating layer and on the top surface of the portion of the porous region, such that there remains a bottom electrode layer inside pores of the portion of the porous region; forming an intermediate layer comprising a dielectric layer or an ionic conductor; and forming a top electrode layer on the intermediate layer.

Abstract: RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.

Abstract: A semiconductor structure that includes a protruding wall structure that extends from a base surface of a substrate. Corners of the protruding wall structure may be smoothed or rounded to reduce electrical stress within the structure. The protruding wall structure may be partitioned into multiple wall regions disposed along different directions of the substrate to reduce mechanical stress.

Abstract: A method of forming an integrated component, for example a capacitor or an ionic capacitor, including: forming a stacked structure on a substrate, the stacked structure having a bottom electrode, an intermediate layer including a layer of dielectric material or a layer of ionic conductor, and a top electrode, wherein forming the top and/or the bottom electrode comprises forming a liner layer of material; and forming a metallic layer on the liner layer, the metallic layer including a noble metal, and wherein the metallic layer is thicker than the liner layer.

Abstract: An integrated electrical device that includes an energy storage component, the component having, above a support, a bottom electrode layer, an intermediate layer having a dielectric layer or an ionic conductor layer above the bottom electrode layer, and a top electrode layer above and on the intermediate layer, wherein the intermediate layer is in contact with the bottom electrode layer and with the top electrode layer in a central region, and the intermediate layer is are spaced apart from either the bottom electrode layer or the top electrode layer by a buffer layer in a peripheral region that surrounds the central region, the buffer layer including an insulating material and arranged on the bottom electrode layer or on the intermediate layer, the buffer layer having an opening that opens onto the bottom electrode layer or onto the intermediate layer so as to define the central region.

Abstract: An electrical device that includes: a capacitor including: a cathode, an anode, and a dielectric structure interposed between the cathode and the anode, wherein the dielectric structure includes a stack of dielectric layers including: a dielectric layer in contact with the cathode, and one or more other dielectric layers, and wherein a product of a dielectric strength (Ecrit121) and a permittivity (?r121) of the dielectric layer in contact with the cathode is greater than a product of a dielectric strength (Ecrit122, Ecrit123) and a permittivity (?r122, ?r123) of each of the one or more other dielectric layers.

Abstract: An electrical device having a capacitor including: a bottom electrode having a conductive structure, the conductive structure having a base surface and protruding walls, wherein the base surface of the conductive structure of the bottom electrode is lower than a top surface of the protruding walls and the base surface surrounds the protruding walls; a dielectric structure extending conformally over the bottom electrode; a top electrode extending conformally over the dielectric structure and having a stack of layers including a first conductive layer and a second conductive layer, wherein the second conductive layer has an opposite intrinsic mechanical stress compared to an intrinsic mechanical stress induced by the first conductive layer and the dielectric structure.

Abstract: An electronic component comprising a 3D capacitive structure includes a substrate having a contoured surface comprising a plurality of wells extending from the surface into the substrate body, a dielectric formed over, and conforming to the shape of, the contoured surface, and a first electrode formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes a second electrode and the dielectric is interposed between it and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and contact an insulating layer formed under the substrate, reducing the electrostatic field arising in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The openings at the bottom of the wells are obturated by the dielectric, defining blind holes within the wells, and the first electrode is in the blind holes.

Abstract: A semi-conductor structure with a crack-blocking three-dimensional structure is described. The semiconductor structure includes a substrate; a functional circuit structure disposed in an area of the substrate; and a three-dimensional structure having at least one continuous trench that extends perpendicularly towards a base surface of the substrate and that surrounds the area of the substrate containing the functional circuit structure.

Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.

Abstract: A semi-conductor structure with a crack-blocking three-dimensional structure is described. The semiconductor structure includes a substrate; a functional circuit structure disposed in an area of the substrate; and a three-dimensional structure having at least one continuous trench that extends perpendicularly towards a base surface of the substrate and that surrounds the area of the substrate containing the functional circuit structure.

Abstract: A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Abstract: An electrical device that includes a capacitor with a monolithic diamond region having: a diamond substrate; a first electrode layer on the diamond substrate; an intermediate layer on the first electrode layer having a dislocation density comprised between 105.cm ?2 to 109.cm?2; and a second electrode layer on the intermediate layer, wherein the first electrode layer and the second electrode layer are doped with p-type impurities and the intermediate layer is doped with a deep level dopant of type n that passivates the dislocations of the intermediate layer, such that the capacitor is formed by the monolithic diamond region between the stack formed by the first electrode layer and the second electrode layer separated by the intermediate layer.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Abstract: An electrical device for high-voltage applications and a method for obtaining an electrical device. The electrical device includes a capacitor having: a bottom electrode having a conductive structure, the conductive structure including a base surface and facing protruding walls extending upwards and having a highest surface; a top electrode having at least one conductive region arranged between the facing protruding walls and having a top surface, wherein the top surface of the at least one conductive region lies below or at the level of the highest surface of the protruding walls; and a dielectric region extending conformally over the bottom electrode and surrounding the top electrode, the capacitor being formed by the bottom and top electrodes separated by the dielectric region.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.