Patents by Inventor Larry Cook
Larry Cook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11633752Abstract: A paint booth assembly includes a paint booth having a pair of side walls and a flood sheet extending between the pair of side walls to separate the paint booth between a spray portion disposed above the flood sheet and a paint recovery portion disposed below the flood sheet. The flood sheet defines at least one flood sheet opening, and a scrubber unit extends down from the flood sheet opening to establish a shared path of fluid communication of a flow of water from the flood sheet and a downdraft of process air from the spray portion to the paint recovery portion. A scrubber pod is disposed within the scrubber unit and defines a plurality of perforations to induce an initial mixing of the paint particles entrained in the downdraft of process air into the flow of water.Type: GrantFiled: July 9, 2021Date of Patent: April 25, 2023Assignee: GALLAGHER-KAISER CORPORATIONInventors: Adrien de Borchgrave, Bruce Roesler, Larry Cook, Ken Eisbrenner
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Publication number: 20210331194Abstract: A paint booth assembly includes a paint booth having a pair of side walls and a flood sheet extending between the pair of side walls to separate the paint booth between a spray portion disposed above the flood sheet and a paint recovery portion disposed below the flood sheet. The flood sheet defines at least one flood sheet opening, and a scrubber unit extends down from the flood sheet opening to establish a shared path of fluid communication of a flow of water from the flood sheet and a downdraft of process air from the spray portion to the paint recovery portion. A scrubber pod is disposed within the scrubber unit and defines a plurality of perforations to induce an initial mixing of the paint particles entrained in the downdraft of process air into the flow of water.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventors: Adrien de Borchgrave, Bruce Roesler, Larry Cook, Ken Eisbrenner
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Patent number: 11084058Abstract: A paint booth assembly includes a paint booth having a pair of side walls and a flood sheet extending between the pair of side walls to separate the paint booth between a spray portion disposed above the flood sheet and a paint recovery portion disposed below the flood sheet. The flood sheet defines at least one flood sheet opening, and a scrubber unit extends down from the flood sheet opening to establish a shared path of fluid communication of a flow of water from the flood sheet and a downdraft of process air from the spray portion to the paint recovery portion. A scrubber pod is disposed within the scrubber unit and defines a plurality of perforations to induce an initial mixing of the paint particles entrained in the downdraft of process air into the flow of water.Type: GrantFiled: October 1, 2019Date of Patent: August 10, 2021Assignee: GALLAGHER-KAISER CORPORATIONInventors: Adrien de Borchgrave, Bruce Roesler, Larry Cook, Ken Eisbrenner
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Publication number: 20200101482Abstract: A paint booth assembly includes a paint booth having a pair of side walls and a flood sheet extending between the pair of side walls to separate the paint booth between a spray portion disposed above the flood sheet and a paint recovery portion disposed below the flood sheet. The flood sheet defines at least one flood sheet opening, and a scrubber unit extends down from the flood sheet opening to establish a shared path of fluid communication of a flow of water from the flood sheet and a downdraft of process air from the spray portion to the paint recovery portion. A scrubber pod is disposed within the scrubber unit and defines a plurality of perforations to induce an initial mixing of the paint particles entrained in the downdraft of process air into the flow of water.Type: ApplicationFiled: October 1, 2019Publication date: April 2, 2020Inventors: Adrien de Borchgrave, Bruce Roesler, Larry Cook, Ken Eisbrenner
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Publication number: 20150088365Abstract: A device that performs real-time continuous data extraction from an Engine Control Module to process the data on a portable, full-function, small-size computer in a driver's compartment of a motor vehicle. The device that formats and displays data, calculates results and distributes reports to a variety of visual display devices for viewing in the driver's compartment by an operator of a vehicle while driving. A device that produces inspection reports for mechanics, regulators and drivers, real-time emission test results on demand and live vehicle performance reporting.Type: ApplicationFiled: September 20, 2014Publication date: March 26, 2015Inventors: Larry Cook, M. Grant Sharp
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Publication number: 20090127866Abstract: The present invention provides, in one embodiment, a device for producing electricity, the device including a housing having a volume of fluid therein, a rotor within the housing, the rotor being in fluid communication with the housing and fixedly attached to a shaft. At least one buoy is sized and shaped to move through the fluid in housing, as well as though an inlet and outlet of the housing. An electrical generator is coupled to the shaft to which the rotor is attached. When a buoy moved into the housing through the inlet, it rises in the fluid and is received by the rotor, causing the rotor to turn as the buoy continues to rise. The turning of the rotor operates the electrical generator.Type: ApplicationFiled: November 17, 2008Publication date: May 21, 2009Inventor: Larry COOK
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Publication number: 20050218575Abstract: A vacuum workholding system employs vacuum disks and enables modular flexibility in setting up work pieces, such as wing skins, for machining.Type: ApplicationFiled: November 24, 2004Publication date: October 6, 2005Inventors: Larry Cook, Bob Samack
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Patent number: 6725432Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: April 20, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6701504Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: March 2, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6698002Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: February 24, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6694501Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: February 17, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6631470Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: October 7, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6629293Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: February 23, 2001Date of Patent: September 30, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6594800Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: July 15, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20030115564Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: March 23, 2001Publication date: June 19, 2003Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6574778Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: June 3, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6567957Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: May 20, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20020166098Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: March 23, 2001Publication date: November 7, 2002Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20020016952Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: January 4, 2001Publication date: February 7, 2002Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20010042237Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: February 23, 2001Publication date: November 15, 2001Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani