Abstract: A metal interconnect fabrication process for hybrid solid state systems such as thermal imaging system (50). A plurality of vias (62) are formed in a focal plane array (60) between the thermal sensors (20) to expose a corresponding array of contact pads (84) on a silicon processor (80) bonded to the focal plane array (60). A metal film layer (30) is disposed on the focal plane array (60) to fill the vias (62). Photoresist material (32) is patterned on the metal layer (30) to correspond with the desired sensor signal flow path. With the photoresist material (32) still in place, the metal layer (30) is dry etched to produce the desired metal interconnect pattern by removing portions of the metal layer (30) unprotected by the photoresist material (32).

Abstract: Method of manufacturing an infrared detector having a refractory metal (16) within the metal-insulator-semiconductor structure (MIS) provides a process applicable for high volume production of infrared focal plane array detectors. The process of the present invention uses a refractory metal such as tantalum as the gate (16) which is less susceptible to the etching by the bromine solution used to etch the vias (22) as compared to aluminum. Additionally, the etching of the refractory metal film to form the MIS structure can be done with a fluorine-containing plasma, thus avoiding the corrosion of the metal associated with etching aluminum metal films in a chlorine-containing plasma.

Abstract: A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.

Abstract: Method of manufacturing an infrared detector having a refractory metal (16) within the metal-insulator-semiconductor structure (MIS) provides a process applicable for high volume production of infrared focal plane array detectors. The process of the present invention uses a refractory metal such as tantalum as the gate (16) which is less susceptible to the etching by the bromine solution used to etch the vias (22) as compared to aluminum. Additionally, the etching of the refractory metal film to form the MIS structure can be done with a fluorine-containing plasma, thus avoiding the corrosion of the metal associated with etching aluminum metal films in a chlorine-containing plasma.

Abstract: The deposition of zinc sulfide films (16) using dimethylzinc (46) and hydrogen sulfide (44) in a vacuum processor reactor (50) provides a low temperature process applicable for high volume production of infrared focal planes. These layers (16) of zinc sulfide are used as insulators and infrared anti-reflective coatings which are free of contamination relative to physical vapor deposited ZnS films. The zinc sulfide layers (16) are formed by evacuating a chamber (62) and mixing hydrogen sulfide gas (44) and dimethylzinc gas (46) at specific operating conditions until the desired ZnS film thickness is obtained. The rate of growth of the zinc sulfide (16) film is controlled by varying the temperature, pressure, and the relative flow rates of the hydrogen sulfide gas (44) and the dimethylzinc gas (46).

Abstract: A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.